Lines Matching refs:BIT
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
36 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMDA BIT(0)
50 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_XMIEN BIT(7)
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
54 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_ZMIEN BIT(5)
56 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_PP_OD BIT(4)
58 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_IEA BIT(3)
60 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_IEL BIT(2)
62 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_4D BIT(1)
64 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_MIEN BIT(0)
68 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_X BIT(7)
70 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Y BIT(6)
72 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Z BIT(5)
74 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_NTH_X BIT(4)
76 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_NTH_Y BIT(3)
78 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_NTH_Z BIT(2)
80 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_MROI BIT(1)
82 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_MINT BIT(0)
99 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_BOOT BIT(7)
101 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_FIFO_EN BIT(6)
103 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_WTM_EN BIT(5)
105 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_HP_C BIT(2)
107 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_HPIS1 BIT(1)
109 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_HPIS2 BIT(0)
113 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \
114 BIT(4))
116 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_BDU BIT(3)
118 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AZEN BIT(2)
120 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AYEN BIT(1)
122 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AXEN BIT(0)
126 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_ABW (BIT(7) | BIT(6))
128 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_AFS (BIT(5) | BIT(4) | BIT(3))
130 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_AST (BIT(2) | BIT(1))
132 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_SIM BIT(0)
136 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_BOOT BIT(7)
138 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_TAP BIT(6)
140 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INT1 BIT(5)
142 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INT2 BIT(4)
144 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INTM BIT(3)
146 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_DRDYA BIT(2)
148 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_DRDYM BIT(1)
150 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_EMPTY BIT(0)
154 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_TAP BIT(7)
156 #define LMS9DS0_MFD_MASK_CTRL_REG4_XM_P2_INT1 BIT(6)
158 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_INT2 BIT(5)
160 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_INTM BIT(4)
162 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_DRDYA BIT(3)
164 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_DRDYM BIT(2)
166 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_OVR BIT(1)
168 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_WTM BIT(0)
172 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_TEMP_EN BIT(7)
174 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_M_RES (BIT(6) | BIT(5))
176 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_M_ODR (BIT(4) | BIT(3) | BIT(2))
178 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_LIR2 BIT(1)
180 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_LIR1 BIT(0)
184 #define LSM9DS0_MFD_MASK_CTRL_REG6_XM_MFS (BIT(6) | BIT(5))
188 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_AHPM (BIT(7) | BIT(6))
190 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_AFDS BIT(5)
192 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_MLP BIT(2)
194 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_MD (BIT(1) | BIT(0))
198 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZYXAOR BIT(7)
200 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZAOR BIT(6)
202 #define LSM9DS0_MFD_MASK_STATUS_REG_A_YAOR BIT(5)
204 #define LSM9DS0_MFD_MASK_STATUS_REG_A_XAOR BIT(4)
206 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZYXADA BIT(3)
208 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZADA BIT(2)
210 #define LSM9DS0_MFD_MASK_STATUS_REG_A_YADA BIT(1)
212 #define LSM9DS0_MFD_MASK_STATUS_REG_A_XADA BIT(0)
223 #define LSM9DS0_MFD_MASK_FIFO_CTRL_REG_FM (BIT(7) | BIT(6) | BIT(5))
225 #define LSM9DS0_MFD_MASK_FIFO_CTRL_REG_FTH (BIT(4) | BIT(3) | BIT(2) | \
226 BIT(1) | BIT(0))
230 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_WTM BIT(7)
232 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_OVRN BIT(6)
234 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_EMPTY BIT(5)
236 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_FSS (BIT(4) | BIT(3) | BIT(2) | \
237 BIT(1) | BIT(0))
241 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_AOI BIT(7)
243 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_6D BIT(6)
245 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_ZHIE BIT(5)
247 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_ZLIE BIT(4)
249 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_YHIE BIT(3)
251 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_YLIE BIT(2)
253 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_XHIE BIT(1)
255 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_XLIE BIT(0)
259 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_IA BIT(6)
261 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_ZH BIT(5)
263 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_ZL BIT(4)
265 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_YH BIT(3)
267 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_YL BIT(2)
269 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_XH BIT(1)
271 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_XL BIT(0)
275 #define LSM9DS0_MFD_MASK_INT_GEN_1_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
276 BIT(3) | BIT(2) | BIT(1) | \
277 BIT(0))
281 #define LSM9DS0_MFD_MASK_INT_GEN_1_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \
282 BIT(3) | BIT(2) | BIT(1) | \
283 BIT(0))
287 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_AOI BIT(7)
289 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_6D BIT(6)
291 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_ZHIE BIT(5)
293 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_ZLIE BIT(4)
295 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_YHIE BIT(3)
297 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_YLIE BIT(2)
299 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_XHIE BIT(1)
301 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_XLIE BIT(0)
305 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_IA BIT(6)
307 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_ZH BIT(5)
309 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_ZL BIT(4)
311 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_YH BIT(3)
313 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_YL BIT(2)
315 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_XH BIT(1)
317 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_XL BIT(0)
321 #define LSM9DS0_MFD_MASK_INT_GEN_2_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
322 BIT(3) | BIT(2) | BIT(1) | \
323 BIT(0))
327 #define LSM9DS0_MFD_MASK_INT_GEN_2_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \
328 BIT(3) | BIT(2) | BIT(1) | \
329 ensor_ BIT(0))
333 #define LSM9DS0_MFD_MASK_CLICK_CFG_ZD BIT(5)
335 #define LSM9DS0_MFD_MASK_CLICK_CFG_ZS BIT(4)
337 #define LSM9DS0_MFD_MASK_CLICK_CFG_YD BIT(3)
339 #define LSM9DS0_MFD_MASK_CLICK_CFG_YS BIT(2)
341 #define LSM9DS0_MFD_MASK_CLICK_CFG_XD BIT(1)
343 #define LSM9DS0_MFD_MASK_CLICK_CFG_XS BIT(0)
347 #define LSM9DS0_MFD_MASK_CLICK_SRC_IA BIT(6)
349 #define LSM9DS0_MFD_MASK_CLICK_SRC_DC BIT(5)
351 #define LSM9DS0_MFD_MASK_CLICK_SRC_SC BIT(4)
353 #define LSM9DS0_MFD_MASK_CLICK_SRC_S BIT(3)
355 #define LSM9DS0_MFD_MASK_CLICK_SRC_Z BIT(2)
357 #define LSM9DS0_MFD_MASK_CLICK_SRC_Y BIT(1)
359 #define LSM9DS0_MFD_MASK_CLICK_SRC_X BIT(0)
363 #define LSM9DS0_MFD_MASK_CLICK_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
364 BIT(3) | BIT(2) | BIT(1) | \
365 BIT(0))
369 #define LSM9DS0_MFD_MASK_TIME_LIMIT_TLI (BIT(6) | BIT(5) | BIT(4) | \
370 BIT(3) | BIT(2) | BIT(1) | \
371 BIT(0))
375 #define LSM9DS0_MFD_MASK_TIME_LATENCY_TLA (BIT(7) | BIT(6) | BIT(5) | \
376 BIT(4) | BIT(3) | BIT(2) | \
377 BIT(1) | BIT(0))
381 #define LSM9DS0_MFD_MASK_TIME_WINDOW_TW (BIT(7) | BIT(6) | BIT(5) | \
382 BIT(4) | BIT(3) | BIT(2) | \
383 BIT(1) | BIT(0))
387 #define LSM9DS0_MFD_MASK_ACT_THS_ACTHS (BIT(6) | BIT(5) | BIT(4) | \
388 BIT(3) | BIT(2) | BIT(1) | \
389 BIT(0))
393 #define LSM9DS0_MFD_MASK_ACT_DUR_ACTD (BIT(7) | BIT(6) | BIT(5) | \
394 BIT(4) | BIT(3) | BIT(2) | \
395 BIT(1) | BIT(0))