Lines Matching full:6
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
25 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZMOR 6
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
53 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_YMIEN 6
70 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Y BIT(6)
71 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_Y 6
101 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_FIFO_EN BIT(6)
102 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_FIFO_EN 6
113 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \
126 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_ABW (BIT(7) | BIT(6))
127 #define LSM9DS0_MFD_SHIFT_CTRL_REG2_XM_ABW 6
138 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_TAP BIT(6)
139 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_TAP 6
156 #define LMS9DS0_MFD_MASK_CTRL_REG4_XM_P2_INT1 BIT(6)
157 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_INT1 6
174 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_M_RES (BIT(6) | BIT(5))
184 #define LSM9DS0_MFD_MASK_CTRL_REG6_XM_MFS (BIT(6) | BIT(5))
188 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_AHPM (BIT(7) | BIT(6))
189 #define LSM9DS0_MFD_SHIFT_CTRL_REG7_XM_AHPM 6
200 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZAOR BIT(6)
201 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_ZAOR 6
223 #define LSM9DS0_MFD_MASK_FIFO_CTRL_REG_FM (BIT(7) | BIT(6) | BIT(5))
232 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_OVRN BIT(6)
233 #define LSM9DS0_MFD_SHIFT_FIFO_SRC_REG_OVRN 6
243 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_6D BIT(6)
244 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_6D 6
259 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_IA BIT(6)
260 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_IA 6
275 #define LSM9DS0_MFD_MASK_INT_GEN_1_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
281 #define LSM9DS0_MFD_MASK_INT_GEN_1_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \
289 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_6D BIT(6)
290 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_6D 6
305 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_IA BIT(6)
306 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_IA 6
321 #define LSM9DS0_MFD_MASK_INT_GEN_2_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
327 #define LSM9DS0_MFD_MASK_INT_GEN_2_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \
347 #define LSM9DS0_MFD_MASK_CLICK_SRC_IA BIT(6)
348 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_IA 6
363 #define LSM9DS0_MFD_MASK_CLICK_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
369 #define LSM9DS0_MFD_MASK_TIME_LIMIT_TLI (BIT(6) | BIT(5) | BIT(4) | \
375 #define LSM9DS0_MFD_MASK_TIME_LATENCY_TLA (BIT(7) | BIT(6) | BIT(5) | \
381 #define LSM9DS0_MFD_MASK_TIME_WINDOW_TW (BIT(7) | BIT(6) | BIT(5) | \
387 #define LSM9DS0_MFD_MASK_ACT_THS_ACTHS (BIT(6) | BIT(5) | BIT(4) | \
393 #define LSM9DS0_MFD_MASK_ACT_DUR_ACTD (BIT(7) | BIT(6) | BIT(5) | \
416 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 6