Lines Matching full:5
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
27 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_YMOR 5
54 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_ZMIEN BIT(5)
55 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_ZMIEN 5
72 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Z BIT(5)
73 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_Z 5
103 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_WTM_EN BIT(5)
104 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_WTM_EN 5
113 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \
128 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_AFS (BIT(5) | BIT(4) | BIT(3))
140 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INT1 BIT(5)
141 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_INT1 5
158 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_INT2 BIT(5)
159 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_INT2 5
174 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_M_RES (BIT(6) | BIT(5))
175 #define LSM9DS0_MFD_SHIFT_CTRL_REG5_XM_M_RES 5
184 #define LSM9DS0_MFD_MASK_CTRL_REG6_XM_MFS (BIT(6) | BIT(5))
185 #define LSM9DS0_MFD_SHIFT_CTRL_REG6_XM_MFS 5
190 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_AFDS BIT(5)
191 #define LSM9DS0_MFD_SHIFT_CTRL_REG7_XM_AFDS 5
202 #define LSM9DS0_MFD_MASK_STATUS_REG_A_YAOR BIT(5)
203 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_YAOR 5
223 #define LSM9DS0_MFD_MASK_FIFO_CTRL_REG_FM (BIT(7) | BIT(6) | BIT(5))
224 #define LSM9DS0_MFD_SHIFT_FIFO_CTRL_REG_FM 5
234 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_EMPTY BIT(5)
235 #define LMS9DS0_MFD_SHIFT_FIFO_SRC_REG_EMPTY 5
245 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_ZHIE BIT(5)
246 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_ZHIE 5
261 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_ZH BIT(5)
262 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_ZH 5
275 #define LSM9DS0_MFD_MASK_INT_GEN_1_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
281 #define LSM9DS0_MFD_MASK_INT_GEN_1_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \
291 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_ZHIE BIT(5)
292 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_ZHIE 5
307 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_ZH BIT(5)
308 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_ZH 5
321 #define LSM9DS0_MFD_MASK_INT_GEN_2_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
327 #define LSM9DS0_MFD_MASK_INT_GEN_2_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \
333 #define LSM9DS0_MFD_MASK_CLICK_CFG_ZD BIT(5)
334 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_ZD 5
349 #define LSM9DS0_MFD_MASK_CLICK_SRC_DC BIT(5)
350 #define LMS9DS0_MFD_SHIFT_CLICK_SRC_DC 5
363 #define LSM9DS0_MFD_MASK_CLICK_THS_THS (BIT(6) | BIT(5) | BIT(4) | \
369 #define LSM9DS0_MFD_MASK_TIME_LIMIT_TLI (BIT(6) | BIT(5) | BIT(4) | \
375 #define LSM9DS0_MFD_MASK_TIME_LATENCY_TLA (BIT(7) | BIT(6) | BIT(5) | \
381 #define LSM9DS0_MFD_MASK_TIME_WINDOW_TW (BIT(7) | BIT(6) | BIT(5) | \
387 #define LSM9DS0_MFD_MASK_ACT_THS_ACTHS (BIT(6) | BIT(5) | BIT(4) | \
393 #define LSM9DS0_MFD_MASK_ACT_DUR_ACTD (BIT(7) | BIT(6) | BIT(5) | \
413 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 5
476 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 5