Lines Matching refs:BIT
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
40 BIT(0))
43 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
45 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_BOOT BIT(6)
47 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_H_L BIT(5)
49 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_PP_OD BIT(4)
51 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_DRDY BIT(3)
53 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_WTM BIT(2)
55 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_OR BIT(1)
57 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_E BIT(0)
61 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BDU BIT(7)
63 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BLE BIT(6)
65 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_FS (BIT(5) | BIT(4))
67 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_ST (BIT(2) | BIT(1))
71 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_BOOT BIT(7)
73 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_FIFO_EN BIT(6)
75 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_HPEN BIT(4)
77 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_INT1_SEL (BIT(3) | BIT(2))
79 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_OUT_SEL (BIT(1) | BIT(0))
85 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXOR BIT(7)
87 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZOR BIT(6)
89 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_YOR BIT(5)
91 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_XOR BIT(4)
93 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXDA BIT(3)
95 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZDA BIT(2)
97 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_YDA BIT(1)
99 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_XDA BIT(0)
110 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_FM (BIT(7) | BIT(6) | BIT(5))
112 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_WTM (BIT(4) | BIT(3) | BIT(2) | \
113 BIT(1) | BIT(0))
117 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_WTM BIT(7)
119 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_OVRN BIT(6)
121 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_EMPTY BIT(5)
123 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_FSS (BIT(4) | BIT(3) | BIT(2) | \
124 BIT(1) | BIT(0))
128 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_ANDOR BIT(7)
130 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_LIR BIT(6)
132 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_ZHIE BIT(5)
134 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_ZLIE BIT(4)
136 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_YHIE BIT(3)
138 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_YLIE BIT(2)
140 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_XHIE BIT(1)
142 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_XLIE BIT(0)
146 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_IA BIT(6)
148 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_ZH BIT(5)
150 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_ZL BIT(4)
152 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_YH BIT(3)
154 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_YL BIT(2)
156 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_XH BIT(1)
158 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_XL BIT(0)
162 #define LSM9DS0_GYRO_MASK_INT1_THS_XH_G (BIT(6) | BIT(5) | BIT(4) | \
163 BIT(3) | BIT(2) | BIT(1) | \
164 BIT(0))
169 #define LSM9DS0_GYRO_MASK_INT1_THS_YH_G (BIT(6) | BIT(5) | BIT(4) | \
170 BIT(3) | BIT(2) | BIT(1) | \
171 BIT(0))
176 #define LSM9DS0_GYRO_MASK_INT1_THS_ZH_G (BIT(6) | BIT(5) | BIT(4) | \
177 BIT(3) | BIT(2) | BIT(1) | \
178 BIT(0))
183 #define LSM9DS0_GYRO_MASK_INT1_DURATION_G_WAIT BIT(7)
185 #define LSM9DS0_GYRO_MASK_INT1_DURATION_G_D (BIT(6) | BIT(5) | BIT(4) | \
186 BIT(3) | BIT(2) | BIT(1) | \
187 BIT(0))