Lines Matching +full:0 +full:- +full:5
1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
28 #define LSM6DSL_REG_FUNC_CFG_ACCESS 0x01
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
32 #define LSM6DSL_SHIFT_FUNC_CFG_EN_B 5
34 #define LSM6DSL_REG_SENSOR_SYNC_TIME_FRAME 0x04
36 BIT(1) | BIT(0))
37 #define LSM6DSL_SHIFT_SENSOR_SYNC_TIME_FRAME_TPH 0
39 #define LSM6DSL_REG_SENSOR_SYNC_RES_RATIO 0x05
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
41 #define LSM6DSL_SHIFT_SENSOR_SYNC_RES_RATIO 0
43 #define LSM6DSL_REG_FIFO_CTRL1 0x06
45 BIT(5) | BIT(4) | \
47 BIT(1) | BIT(0))
48 #define LSM6DSL_SHIFT_FIFO_CTRL1_FTH 0
50 #define LSM6DSL_REG_FIFO_CTRL2 0x07
58 BIT(0))
59 #define LSM6DSL_SHIFT_FIFO_CTRL2_FTH 0
61 #define LSM6DSL_REG_FIFO_CTRL3 0x08
62 #define LSM6DSL_MASK_FIFO_CTRL3_DEC_FIFO_GYRO (BIT(5) | BIT(4) | \
66 BIT(0))
67 #define LSM6DSL_SHIFT_FIFO_CTRL3_DEC_FIFO_XL 0
69 #define LSM6DSL_REG_FIFO_CTRL4 0x09
74 #define LSM6DSL_MASK_FIFO_CTRL4_DEC_DS4_FIFO (BIT(5) | BIT(4) | \
78 BIT(0))
79 #define LSM6DSL_SHIFT_FIFO_CTRL4_DEC_DS3_FIFO 0
81 #define LSM6DSL_REG_FIFO_CTRL5 0x0A
82 #define LSM6DSL_MASK_FIFO_CTRL5_ODR_FIFO (BIT(6) | BIT(5) | \
86 BIT(0))
87 #define LSM6DSL_SHIFT_FIFO_CTRL5_FIFO_MODE 0
89 #define LSM6DSL_REG_DRDY_PULSE_CFG_G 0x0B
92 #define LSM6DSL_MASK_DRDY_PULSE_CFG_G_INT2_WRIST_TILT BIT(0)
93 #define LSM6DSL_SHIFT_DRDY_PULSE_CFG_G_INT2_WRIST_TILT 0
95 #define LSM6DSL_REG_INT1_CTRL 0x0D
100 #define LSM6DSL_MASK_INT1_CTRL_FULL_FLAG BIT(5)
101 #define LSM6DSL_SHIFT_INT1_CTRL_FULL_FLAG 5
110 #define LSM6DSL_MASK_INT1_CTRL_DRDY_XL BIT(0)
111 #define LSM6DSL_SHIFT_INT1_CTRL_DRDY_XL 0
113 #define LSM6DSL_REG_INT2_CTRL 0x0E
118 #define LSM6DSL_MASK_INT2_CTRL_FULL_FLAG BIT(5)
119 #define LSM6DSL_SHIFT_INT2_CTRL_FULL_FLAG 5
128 #define LSM6DSL_MASK_INT2_CTRL_DRDY_XL BIT(0)
129 #define LSM6DSL_SHIFT_INT2_CTRL_DRDY_XL 0
131 #define LSM6DSL_REG_WHO_AM_I 0x0F
132 #define LSM6DSL_VAL_WHO_AM_I 0x6A
134 #define LSM6DSL_REG_CTRL1_XL 0x10
136 BIT(5) | BIT(4))
143 #define LSM6DSL_REG_CTRL2_G 0x11
145 BIT(5) | BIT(4))
152 #define LSM6DSL_REG_CTRL3_C 0x12
157 #define LSM6DSL_MASK_CTRL3_C_H_LACTIVE BIT(5)
158 #define LSM6DSL_SHIFT_CTRL3_C_H_LACTIVE 5
167 #define LSM6DSL_MASK_CTRL3_C_SW_RESET BIT(0)
168 #define LSM6DSL_SHIFT_CTRL3_C_SW_RESET 0
170 #define LSM6DSL_REG_CTRL4_C 0x13
175 #define LSM6DSL_MASK_CTRL4_C_INT2_ON_INT1 BIT(5)
176 #define LSM6DSL_SHIFT_CTRL4_C_INT2_ON_INT1 5
186 #define LSM6DSL_REG_CTRL5_C 0x14
188 BIT(5))
189 #define LSM6DSL_SHIFT_CTRL5_C_ROUNDING 5
194 #define LSM6DSL_MASK_CTRL5_C_ST_XL (BIT(1) | BIT(0))
195 #define LSM6DSL_SHIFT_CTRL5_C_ST_XL 0
197 #define LSM6DSL_REG_CTRL6_C 0x15
202 #define LSM6DSL_MASK_CTRL6_C_LVL2_EN BIT(5)
203 #define LSM6DSL_SHIFT_CTRL6_C_LVL2_EN 5
208 #define LSM6DSL_MASK_CTRL6_C_FTYPE (BIT(0) | BIT(1))
209 #define LSM6DSL_SHIFT_CTRL6_C_FTYPE 0
211 #define LSM6DSL_REG_CTRL7_G 0x16
216 #define LSM6DSL_MASK_CTRL7_HPM_G (BIT(5) | BIT(4))
221 #define LSM6DSL_REG_CTRL8_XL 0x17
224 #define LSM6DSL_MASK_CTRL8_HPCF_XL (BIT(6) | BIT(5))
225 #define LSM6DSL_SHIFT_CTRL8_HPCF_XL 5
232 #define LSM6DSL_MASK_CTRL8_LOW_PASS_ON_6D BIT(0)
233 #define LSM6DSL_SHIFT_CTRL8_LOW_PASS_ON_6D 0
235 #define LSM6DSL_REG_CTRL9_XL 0x18
240 #define LSM6DSL_MASK_CTRL9_XL_DEN_Z BIT(5)
241 #define LSM6DSL_SHIFT_CTRL9_XL_DEN_Z 5
247 #define LSM6DSL_REG_CTRL10_C 0x19
250 #define LSM6DSL_MASK_CTRL10_C_TIMER_EN BIT(5)
251 #define LSM6DSL_SHIFT_CTRL10_C_TIMER_EN 5
260 #define LSM6DSL_MASK_CTRL10_C_SIGN_MOTION_EN BIT(0)
261 #define LSM6DSL_SHIFT_CTRL10_C_SIGN_MOTION_EN 0
263 #define LSM6DSL_REG_MASTER_CONFIG 0x1A
276 #define LSM6DSL_MASK_MASTER_CONFIG_MASTER_ON BIT(0)
277 #define LSM6DSL_SHIFT_MASTER_CONFIG_MASTER_ON 0
279 #define LSM6DSL_REG_WAKE_UP_SRC 0x1B
280 #define LSM6DSL_MASK_WAKE_UP_SRC_FF_IA BIT(5)
281 #define LSM6DSL_SHIFT_WAKE_UP_SRC_FF_IA 5
290 #define LSM6DSL_MASK_WAKE_UP_SRC_Z_WU BIT(0)
291 #define LSM6DSL_SHIFT_WAKE_UP_SRC_Z_WU 0
293 #define LSM6DSL_REG_TAP_SRC 0x1C
296 #define LSM6DSL_MASK_TAP_SRC_SINGLE_TAP BIT(5)
297 #define LSM6DSL_SHIFT_TAP_SRC_SINGLE_TAP 5
306 #define LSM6DSL_MASK_TAP_SRC_Z_TAP BIT(0)
307 #define LSM6DSL_SHIFT_TAP_SRC_Z_TAP 0
309 #define LSM6DSL_REG_D6D_SRC 0x1D
314 #define LSM6DSL_MASK_D6D_SRC_ZH BIT(5)
315 #define LSM6DSL_SHIFT_D6D_SRC_ZH 5
324 #define LSM6DSL_MASK_D6D_SRC_XL BIT(0)
325 #define LSM6DSL_SHIFT_D6D_SRC_XL 0
327 #define LSM6DSL_REG_STATUS_REG 0x1E
332 #define LSM6DSL_MASK_STATUS_REG_XLDA BIT(0)
333 #define LSM6DSL_SHIFT_STATUS_REG_XLDA 0
335 #define LSM6DSL_REG_OUT_TEMP_L 0x20
336 #define LSM6DSL_REG_OUT_TEMP_H 0x21
337 #define LSM6DSL_REG_OUTX_L_G 0x22
338 #define LSM6DSL_REG_OUTX_H_G 0x23
339 #define LSM6DSL_REG_OUTY_L_G 0x24
340 #define LSM6DSL_REG_OUTY_H_G 0x25
341 #define LSM6DSL_REG_OUTZ_L_G 0x26
342 #define LSM6DSL_REG_OUTZ_H_G 0x27
343 #define LSM6DSL_REG_OUTX_L_XL 0x28
344 #define LSM6DSL_REG_OUTX_H_XL 0x29
345 #define LSM6DSL_REG_OUTY_L_XL 0x2A
346 #define LSM6DSL_REG_OUTY_H_XL 0x2B
347 #define LSM6DSL_REG_OUTZ_L_XL 0x2C
348 #define LSM6DSL_REG_OUTZ_H_XL 0x2D
349 #define LSM6DSL_REG_SENSORHUB1 0x2E
350 #define LSM6DSL_REG_SENSORHUB2 0x2F
351 #define LSM6DSL_REG_SENSORHUB3 0x30
352 #define LSM6DSL_REG_SENSORHUB4 0x31
353 #define LSM6DSL_REG_SENSORHUB5 0x32
354 #define LSM6DSL_REG_SENSORHUB6 0x33
355 #define LSM6DSL_REG_SENSORHUB7 0x34
356 #define LSM6DSL_REG_SENSORHUB8 0x35
357 #define LSM6DSL_REG_SENSORHUB9 0x36
358 #define LSM6DSL_REG_SENSORHUB10 0x37
359 #define LSM6DSL_REG_SENSORHUB11 0x38
360 #define LSM6DSL_REG_SENSORHUB12 0x39
361 #define LSM6DSL_REG_FIFO_STATUS1 0x3A
363 #define LSM6DSL_REG_FIFO_STATUS2 0x3B
368 #define LSM6DSL_MASK_FIFO_STATUS2_FIFO_FULL_SMART BIT(5)
369 #define LSM6DSL_SHIFT_FIFO_STATUS2_FIFO_FULL_SMART 5
373 BIT(0))
374 #define LSM6DSL_SHIFT_FIFO_STATUS2_DIFF_FIFO 0
376 #define LSM6DSL_REG_FIFO_STATUS3 0x3C
377 #define LSM6DSL_MASK_FIFO_STATUS3_FIFO_PATTERN 0xFF
378 #define LSM6DSL_SHIFT_FIFO_STATUS3_FIFO_PATTERN 0
380 #define LSM6DSL_REG_FIFO_STATUS4 0x3D
381 #define LSM6DSL_MASK_FIFO_STATUS4_FIFO_PATTERN (BIT(1) | BIT(0))
382 #define LSM6DSL_SHIFT_FIFO_STATUS4_FIFO_PATTERN 0
384 #define LSM6DSL_REG_FIFO_DATA_OUT_L 0x3E
385 #define LSM6DSL_REG_FIFO_DATA_OUT_H 0x3F
386 #define LSM6DSL_REG_TIMESTAMP0 0x40
387 #define LSM6DSL_REG_TIMESTAMP1 0x41
388 #define LSM6DSL_REG_TIMESTAMP2 0x42
389 #define LSM6DSL_REG_STEP_TIMESTAMP_L 0x49
390 #define LSM6DSL_REG_STEP_TIMESTAMP_H 0x4A
391 #define LSM6DSL_REG_STEP_COUNTER_L 0x4B
392 #define LSM6DSL_REG_STEP_COUNTER_H 0x4C
393 #define LSM6DSL_REG_SENSORHUB13 0x4D
394 #define LSM6DSL_REG_SENSORHUB14 0x4E
395 #define LSM6DSL_REG_SENSORHUB15 0x4F
396 #define LSM6DSL_REG_SENSORHUB16 0x50
397 #define LSM6DSL_REG_SENSORHUB17 0x51
398 #define LSM6DSL_REG_SENSORHUB18 0x52
400 #define LSM6DSL_REG_FUNC_SRC1 0x53
405 #define LSM6DSL_MASK_FUNC_SRC1_TILT_IA BIT(5)
406 #define LSM6DSL_SHIFT_FUNC_SRC1_TILT_IA 5
415 #define LSM6DSL_MASK_FUNC_SRC1_SENSORHUB_END_OP BIT(0)
416 #define LSM6DSL_SHIFT_FUNC_SRC1_SENSORHUB_END_OP 0
418 #define LSM6DSL_REG_FUNC_SRC2 0x54
421 #define LSM6DSL_MASK_FUNC_SRC2_SLAVE2_NACK BIT(5)
422 #define LSM6DSL_SHIFT_FUNC_SRC2_SLAVE2_NACK 5
427 #define LSM6DSL_MASK_FUNC_SRC2_WRIST_TILT_IA BIT(0)
428 #define LSM6DSL_SHIFT_FUNC_SRC2_WRIST_TILT_IA 0
430 #define LSM6DSL_REG_WRIST_TILT_IA 0x55
435 #define LSM6DSL_MASK_WRIST_TILT_IA_YPOS BIT(5)
436 #define LSM6DSL_SHIFT_WRIST_TILT_IA_YPOS 5
444 #define LSM6DSL_REG_TAP_CFG 0x58
447 #define LSM6DSL_MASK_TAP_CFG_INACT_EN (BIT(6) | BIT(5))
448 #define LSM6DSL_SHIFT_TAP_CFG_INACT_EN 5
457 #define LSM6DSL_MASK_TAP_CFG_LIR BIT(0)
458 #define LSM6DSL_SHIFT_TAP_CFG_LIR 0
460 #define LSM6DSL_REG_TAP_THS_6D 0x59
463 #define LSM6DSL_MASK_TAP_THS_6D_SIXD_THS (BIT(6) | BIT(5))
464 #define LSM6DSL_SHIFT_TAP_THS_6D_SIXD_THS 5
467 BIT(0))
468 #define LSM6DSL_SHIFT_TAP_THS_6D_TAP_THS 0
470 #define LSM6DSL_REG_INT_DUR2 0x5A
472 BIT(5) | BIT(4))
476 #define LSM6DSL_MASK_INT_DUR2_SHOCK (BIT(1) | BIT(0))
477 #define LSM6DSL_SHIFT_INT_SHOCK 0
479 #define LSM6DSL_REG_WAKE_UP_THS 0x5B
482 #define LSM6DSL_MASK_WAKE_UP_THS_WK_THS (BIT(5) | BIT(4) | \
484 BIT(1) | BIT(0))
485 #define LSM6DSL_SHIFT_WAKE_UP_THS_WK_THS 0
487 #define LSM6DSL_REG_WAKE_UP_DUR 0x5C
490 #define LSM6DSL_MASK_WAKE_UP_DUR_WAKE_DUR (BIT(6) | BIT(5))
491 #define LSM6DSL_SHIFT_WAKE_UP_DUAR_WAKE_DUR 5
495 BIT(1) | BIT(0))
496 #define LSM6DSL_SHIFT_WAKE_UP_DUR_SLEEP_DUR 0
498 #define LSM6DSL_REG_FREE_FALL 0x5D
500 BIT(5) | BIT(4) | \
504 BIT(0))
505 #define LSM6DSL_SHIFT_FREE_FALL_THS 0
507 #define LSM6DSL_REG_MD1_CFG 0x5E
512 #define LSM6DSL_MASK_MD1_CFG_INT1_WU BIT(5)
513 #define LSM6DSL_SHIFT_MD1_CFG_INT1_WU 5
522 #define LSM6DSL_MASK_MD1_CFG_INT1_TIMER BIT(0)
523 #define LSM6DSL_SHIFT_MD1_CFG_INT1_TIMER 0
525 #define LSM6DSL_REG_MD2_CFG 0x5F
530 #define LSM6DSL_MASK_MD2_CFG_INT2_WU BIT(5)
531 #define LSM6DSL_SHIFT_MD2_CFG_INT2_WU 5
540 #define LSM6DSL_MASK_MD2_CFG_INT2_IRON BIT(0)
541 #define LSM6DSL_SHIFT_MD2_CFG_INT2_IRON 0
543 #define LSM6DSL_REG_MASTER_CMD_CODE 0x60
544 #define LSM6DSL_REG_SENS_SYNC_SPI_ERROR_CODE 0x61
545 #define LSM6DSL_REG_OUT_MAG_RAW_X_L 0x66
546 #define LSM6DSL_REG_OUT_MAG_RAW_X_H 0x67
547 #define LSM6DSL_REG_OUT_MAG_RAW_Y_L 0x68
548 #define LSM6DSL_REG_OUT_MAG_RAW_Y_H 0x69
549 #define LSM6DSL_REG_OUT_MAG_RAW_Z_L 0x6A
550 #define LSM6DSL_REG_OUT_MAG_RAW_Z_H 0x6B
551 #define LSM6DSL_REG_X_OFS_USR 0x73
552 #define LSM6DSL_REG_Y_OFS_USR 0x74
553 #define LSM6DSL_REG_Z_OFS_USR 0x75
562 #if CONFIG_LSM6DSL_ACCEL_FS == 0
564 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 0
567 #define LSM6DSL_DEFAULT_ACCEL_FULLSCALE 0
580 #if (CONFIG_LSM6DSL_ACCEL_ODR == 0)
586 #if CONFIG_LSM6DSL_GYRO_FS == 0
594 #define LSM6DSL_DEFAULT_GYRO_FULLSCALE 0
608 #if (CONFIG_LSM6DSL_GYRO_ODR == 0)