Lines Matching full:bit
19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
37 #define LSM6DS0_MASK_INT_GEN_CFG_XL_YHIE_XL BIT(3)
39 #define LSM6DS0_MASK_INT_GEN_CFG_XL_YLIE_XL BIT(2)
41 #define LSM6DS0_MASK_INT_GEN_CFG_XL_XHIE_XL BIT(1)
43 #define LSM6DS0_MASK_INT_GEN_CFG_XL_XLIE_XL BIT(0)
53 #define LSM6DS0_MASK_INT_CTRL_INT_IG_G BIT(7)
55 #define LSM6DS0_MASK_INT_CTRL_INT_IG_XL BIT(6)
57 #define LSM6DS0_MASK_INT_CTRL_INT_FSS5 BIT(5)
59 #define LSM6DS0_MASK_INT_CTRL_INT_OVR BIT(4)
61 #define LSM6DS0_MASK_INT_CTRL_INT_FTH BIT(3)
63 #define LSM6DS0_MASK_INT_CTRL_INT_BOOT BIT(2)
65 #define LSM6DS0_MASK_INT_CTRL_INT_DRDY_G BIT(1)
67 #define LSM6DS0_MASK_INT_CTRL_INT_DRDY_XL BIT(0)
74 #define LSM6DS0_MASK_CTRL_REG1_G_ODR_G (BIT(7) | BIT(6) | BIT(5))
76 #define LSM6DS0_MASK_CTRL_REG1_G_FS_G (BIT(4) | BIT(3))
78 #define LSM6DS0_MASK_CTRL_REG1_G_BW_G (BIT(1) | BIT(0))
82 #define LSM6DS0_MASK_CTRL_REG2_G_INT_SEL (BIT(3) | BIT(2))
84 #define LSM6DS0_MASK_CTRL_REG2_G_OUT_SEL (BIT(1) | BIT(0))
88 #define LSM6DS0_MASK_CTRL_REG3_G_LP_MODE BIT(7)
90 #define LSM6DS0_MASK_CTRL_REG3_G_HP_EN BIT(6)
92 #define LSM6DS0_MASK_CTRL_REG3_G_HPCF_G (BIT(3) | BIT(2) | BIT(1) | \
93 BIT(0))
97 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNX_G BIT(5)
99 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNY_G BIT(4)
101 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNZ_G BIT(3)
103 #define LSM6DS0_MASK_ORIENT_CFG_ORIENT (BIT(2) | BIT(1) | BIT(0))
107 #define LSM6DS0_MASK_INT_GEN_SRC_G_IA_G BIT(6)
109 #define LSM6DS0_MASK_INT_GEN_SRC_G_ZH_G BIT(5)
111 #define LSM6DS0_MASK_INT_GEN_SRC_G_ZL_G BIT(4)
113 #define LSM6DS0_MASK_INT_GEN_SRC_G_YH_G BIT(3)
115 #define LSM6DS0_MASK_INT_GEN_SRC_G_YL_G BIT(2)
117 #define LSM6DS0_MASK_INT_GEN_SRC_G_XH_G BIT(1)
119 #define LSM6DS0_MASK_INT_GEN_SRC_G_XL_G BIT(0)
126 #define LSM6DS0_MASK_STATUS_REG_G_IG_XL BIT(6)
128 #define LSM6DS0_MASK_STATUS_REG_G_IG_G BIT(5)
130 #define LSM6DS0_MASK_STATUS_REG_G_INACT BIT(4)
132 #define LSM6DS0_MASK_STATUS_REG_G_BOOT_STATUS BIT(3)
134 #define LSM6DS0_MASK_STATUS_REG_G_TDA BIT(2)
136 #define LSM6DS0_MASK_STATUS_REG_G_GDA BIT(1)
138 #define LSM6DS0_MASK_STATUS_REG_G_XLDA BIT(0)
149 #define LSM6DS0_MASK_CTRL_REG4_ZEN_G BIT(5)
151 #define LSM6DS0_MASK_CTRL_REG4_YEN_G BIT(4)
153 #define LSM6DS0_MASK_CTRL_REG4_XEN_G BIT(3)
155 #define LSM6DS0_MASK_CTRL_REG4_LIR_XL1 BIT(1)
157 #define LSM6DS0_MASK_CTRL_REG4_4D_XL1 BIT(0)
161 #define LSM6DS0_MASK_CTRL_REG5_XL_DEC (BIT(7) | BIT(6))
163 #define LSM6DS0_MASK_CTRL_REG5_XL_ZEN_XL BIT(5)
165 #define LSM6DS0_MASK_CTRL_REG5_XL_YEN_XL BIT(4)
167 #define LSM6DS0_MASK_CTRL_REG5_XL_XEN_XL BIT(3)
171 #define LSM6DS0_MASK_CTRL_REG6_XL_ODR_XL (BIT(7) | BIT(6) | BIT(5))
173 #define LSM6DS0_MASK_CTRL_REG6_XL_FS_XL (BIT(4) | BIT(3))
175 #define LSM6DS0_MASK_CTRL_REG6_XL_BW_SCAL_ODR BIT(2)
177 #define LSM6DS0_MASK_CTRL_REG6_XL_BW_XL (BIT(1) | BIT(0))
181 #define LSM6DS0_MASK_CTRL_REG7_XL_HR BIT(7)
183 #define LSM6DS0_MASK_CTRL_REG7_XL_DCF (BIT(6) | BIT(5))
185 #define LSM6DS0_MASK_CTRL_REG7_XL_FDS BIT(2)
187 #define LSM6DS0_MASK_CTRL_REG7_XL_HPIS1 BIT(0)
191 #define LSM6DS0_MASK_CTRL_REG8_BOOT BIT(7)
193 #define LSM6DS0_MASK_CTRL_REG8_BDU BIT(6)
195 #define LSM6DS0_MASK_CTRL_REG8_H_LACTIVE BIT(5)
197 #define LSM6DS0_MASK_CTRL_REG8_PP_OD BIT(4)
199 #define LSM6DS0_MASK_CTRL_REG8_SIM BIT(3)
201 #define LSM6DS0_MASK_CTRL_REG8_IF_ADD_INC BIT(2)
203 #define LSM6DS0_MASK_CTRL_REG8_BLE BIT(1)
205 #define LSM6DS0_MASK_CTRL_REG8_SW_RESET BIT(0)
209 #define LSM6DS0_MASK_CTRL_REG9_SLEEP_G BIT(6)
211 #define LSM6DS0_MASK_CTRL_REG9_FIFO_TEMP_EN BIT(4)
213 #define LSM6DS0_MASK_CTRL_REG9_DRDY_MASK_BIT BIT(3)
215 #define LSM6DS0_MASK_CTRL_REG9_DRDY_I2C_DIS BIT(2)
217 #define LSM6DS0_MASK_CTRL_REG9_FIFO_EN BIT(1)
219 #define LSM6DS0_MASK_CTRL_REG9_STOP_ON_FTH BIT(0)
223 #define LSM6DS0_MASK_CTRL_REG10_ST_G BIT(2)
225 #define LSM6DS0_MASK_CTRL_REG10_ST_XL BIT(0)
229 #define LSM6DS0_MASK_INT_GEN_SRC_XL_IA_XL BIT(6)
231 #define LSM6DS0_MASK_INT_GEN_SRC_XL_ZH_XL BIT(5)
233 #define LSM6DS0_MASK_INT_GEN_SRC_XL_ZL_XL BIT(4)
235 #define LSM6DS0_MASK_INT_GEN_SRC_XL_YH_XL BIT(3)
237 #define LSM6DS0_MASK_INT_GEN_SRC_XL_YL_XL BIT(2)
239 #define LSM6DS0_MASK_INT_GEN_SRC_XL_XH_XL BIT(1)
241 #define LSM6DS0_MASK_INT_GEN_SRC_XL_XL_XL BIT(0)
245 #define LSM6DS0_MASK_STATUS_REG_XL_IG_XL BIT(6)
247 #define LSM6DS0_MASK_STATUS_REG_XL_IG_G BIT(5)
249 #define LSM6DS0_MASK_STATUS_REG_XL_INACT BIT(4)
251 #define LSM6DS0_MASK_STATUS_REG_XL_BOOT_STATUS BIT(3)
253 #define LSM6DS0_MASK_STATUS_REG_XL_TDA BIT(2)
255 #define LSM6DS0_MASK_STATUS_REG_XL_GDA BIT(1)
257 #define LSM6DS0_MASK_STATUS_REG_XL_XLDA BIT(0)
268 #define LSM6DS0_MASK_FIFO_CTRL_FMODE (BIT(7) | BIT(6) | BIT(5))
270 #define LSM6DS0_MASK_FIFO_CTRL_FTH (BIT(4) | BIT(3) | BIT(2) | \
271 BIT(1) | BIT(0))
275 #define LSM6DS0_MASK_FIFO_SRC_FTH BIT(7)
277 #define LSM6DS0_MASK_FIFO_SRC_OVRN BIT(6)
279 #define LSM6DS0_MASK_FIFO_SRC_FSS (BIT(5) | BIT(4) | BIT(3) | \
280 BIT(2) | BIT(1) | BIT(0))
284 #define LSM6DS0_MASK_INT_GEN_CFG_G_AOI_G BIT(7)
286 #define LSM6DS0_MASK_INT_GEN_CFG_G_LIR_G BIT(6)
288 #define LSM6DS0_MASK_INT_GEN_CFG_G_ZHIE_G BIT(5)
290 #define LSM6DS0_MASK_INT_GEN_CFG_G_ZLIE_G BIT(4)
292 #define LSM6DS0_MASK_INT_GEN_CFG_G_YHIE_G BIT(3)
294 #define LSM6DS0_MASK_INT_GEN_CFG_G_YLIE_G BIT(2)
296 #define LSM6DS0_MASK_INT_GEN_CFG_G_XHIE_G BIT(1)
298 #define LSM6DS0_MASK_INT_GEN_CFG_G_XLIE_G BIT(0)
302 #define LSM6DS0_MASK_INT_GEN_THS_XH_G_DCRM_G BIT(7)
312 #define LSM6DS0_MASK_INT_GEN_DUR_G_WAIT_G BIT(7)