Lines Matching full:5
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
34 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_ZHIE_XL 5
57 #define LSM6DS0_MASK_INT_CTRL_INT_FSS5 BIT(5)
58 #define LSM6DS0_SHIFT_INT_CTRL_INT_FSS5 5
74 #define LSM6DS0_MASK_CTRL_REG1_G_ODR_G (BIT(7) | BIT(6) | BIT(5))
75 #define LSM6DS0_SHIFT_CTRL_REG1_G_ODR_G 5
97 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNX_G BIT(5)
98 #define LSM6DS0_SHIFT_ORIENT_CFG_G_SIGNX_G 5
109 #define LSM6DS0_MASK_INT_GEN_SRC_G_ZH_G BIT(5)
110 #define LSM6DS0_SHIFT_INT_GEN_SRC_G_ZH_G 5
128 #define LSM6DS0_MASK_STATUS_REG_G_IG_G BIT(5)
129 #define LSM6DS0_SHIFT_STATUS_REG_G_IG_G 5
149 #define LSM6DS0_MASK_CTRL_REG4_ZEN_G BIT(5)
150 #define LSM6DS0_SHIFT_CTRL_REG4_ZEN_G 5
163 #define LSM6DS0_MASK_CTRL_REG5_XL_ZEN_XL BIT(5)
164 #define LSM6DS0_SHIFT_CTRL_REG5_XL_ZEN_XL 5
171 #define LSM6DS0_MASK_CTRL_REG6_XL_ODR_XL (BIT(7) | BIT(6) | BIT(5))
172 #define LSM6DS0_SHIFT_CTRL_REG6_XL_ODR_XL 5
183 #define LSM6DS0_MASK_CTRL_REG7_XL_DCF (BIT(6) | BIT(5))
184 #define LSM6DS0_SHIFT_CTRL_REG7_XL_DCF 5
195 #define LSM6DS0_MASK_CTRL_REG8_H_LACTIVE BIT(5)
196 #define LSM6DS0_SHIFT_CTRL_REG8_H_LACTIVE 5
231 #define LSM6DS0_MASK_INT_GEN_SRC_XL_ZH_XL BIT(5)
232 #define LSM6DS0_SHIFT_INT_GEN_SRC_XL_ZH_XL 5
247 #define LSM6DS0_MASK_STATUS_REG_XL_IG_G BIT(5)
248 #define LSM6DS0_SHIFT_STATUS_REG_XL_IG_G 5
268 #define LSM6DS0_MASK_FIFO_CTRL_FMODE (BIT(7) | BIT(6) | BIT(5))
269 #define LSM6DS0_SHIFT_FIFO_CTRL_FMODE 5
279 #define LSM6DS0_MASK_FIFO_SRC_FSS (BIT(5) | BIT(4) | BIT(3) | \
288 #define LSM6DS0_MASK_INT_GEN_CFG_G_ZHIE_G BIT(5)
289 #define LSM6DS0_SHIFT_INT_GEN_CFG_G_ZHIE_G 5
406 #define LSM6DS0_DEFAULT_ACCEL_SAMPLING_RATE 5
457 #define LSM6DS0_DEFAULT_GYRO_SAMPLING_RATE 5