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1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
34 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_ZHIE_XL 5
41 #define LSM6DS0_MASK_INT_GEN_CFG_XL_XHIE_XL BIT(1)
42 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_XHIE_XL 1
57 #define LSM6DS0_MASK_INT_CTRL_INT_FSS5 BIT(5)
58 #define LSM6DS0_SHIFT_INT_CTRL_INT_FSS5 5
65 #define LSM6DS0_MASK_INT_CTRL_INT_DRDY_G BIT(1)
66 #define LSM6DS0_SHIFT_INT_CTRL_INT_DRDY_G 1
74 #define LSM6DS0_MASK_CTRL_REG1_G_ODR_G (BIT(7) | BIT(6) | BIT(5))
75 #define LSM6DS0_SHIFT_CTRL_REG1_G_ODR_G 5
78 #define LSM6DS0_MASK_CTRL_REG1_G_BW_G (BIT(1) | BIT(0))
84 #define LSM6DS0_MASK_CTRL_REG2_G_OUT_SEL (BIT(1) | BIT(0))
92 #define LSM6DS0_MASK_CTRL_REG3_G_HPCF_G (BIT(3) | BIT(2) | BIT(1) | \
97 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNX_G BIT(5)
98 #define LSM6DS0_SHIFT_ORIENT_CFG_G_SIGNX_G 5
103 #define LSM6DS0_MASK_ORIENT_CFG_ORIENT (BIT(2) | BIT(1) | BIT(0))
109 #define LSM6DS0_MASK_INT_GEN_SRC_G_ZH_G BIT(5)
110 #define LSM6DS0_SHIFT_INT_GEN_SRC_G_ZH_G 5
117 #define LSM6DS0_MASK_INT_GEN_SRC_G_XH_G BIT(1)
118 #define LSM6DS0_SHIFT_INT_GEN_SRC_G_XH_G 1
128 #define LSM6DS0_MASK_STATUS_REG_G_IG_G BIT(5)
129 #define LSM6DS0_SHIFT_STATUS_REG_G_IG_G 5
136 #define LSM6DS0_MASK_STATUS_REG_G_GDA BIT(1)
137 #define LSM6DS0_SHIFT_STATUS_REG_G_GDA 1
149 #define LSM6DS0_MASK_CTRL_REG4_ZEN_G BIT(5)
150 #define LSM6DS0_SHIFT_CTRL_REG4_ZEN_G 5
155 #define LSM6DS0_MASK_CTRL_REG4_LIR_XL1 BIT(1)
156 #define LSM6DS0_SHIFT_CTRL_REG4_LIR_XL1 1
163 #define LSM6DS0_MASK_CTRL_REG5_XL_ZEN_XL BIT(5)
164 #define LSM6DS0_SHIFT_CTRL_REG5_XL_ZEN_XL 5
171 #define LSM6DS0_MASK_CTRL_REG6_XL_ODR_XL (BIT(7) | BIT(6) | BIT(5))
172 #define LSM6DS0_SHIFT_CTRL_REG6_XL_ODR_XL 5
177 #define LSM6DS0_MASK_CTRL_REG6_XL_BW_XL (BIT(1) | BIT(0))
183 #define LSM6DS0_MASK_CTRL_REG7_XL_DCF (BIT(6) | BIT(5))
184 #define LSM6DS0_SHIFT_CTRL_REG7_XL_DCF 5
195 #define LSM6DS0_MASK_CTRL_REG8_H_LACTIVE BIT(5)
196 #define LSM6DS0_SHIFT_CTRL_REG8_H_LACTIVE 5
203 #define LSM6DS0_MASK_CTRL_REG8_BLE BIT(1)
204 #define LSM6DS0_SHIFT_CTRL_REG8_BLE 1
217 #define LSM6DS0_MASK_CTRL_REG9_FIFO_EN BIT(1)
218 #define LSM6DS0_SHIFT_CTRL_REG9_FIFO_EN 1
231 #define LSM6DS0_MASK_INT_GEN_SRC_XL_ZH_XL BIT(5)
232 #define LSM6DS0_SHIFT_INT_GEN_SRC_XL_ZH_XL 5
239 #define LSM6DS0_MASK_INT_GEN_SRC_XL_XH_XL BIT(1)
240 #define LSM6DS0_SHIFT_INT_GEN_SRC_XL_XH_XL 1
247 #define LSM6DS0_MASK_STATUS_REG_XL_IG_G BIT(5)
248 #define LSM6DS0_SHIFT_STATUS_REG_XL_IG_G 5
255 #define LSM6DS0_MASK_STATUS_REG_XL_GDA BIT(1)
256 #define LSM6DS0_SHIFT_STATUS_REG_XL_GDA 1
268 #define LSM6DS0_MASK_FIFO_CTRL_FMODE (BIT(7) | BIT(6) | BIT(5))
269 #define LSM6DS0_SHIFT_FIFO_CTRL_FMODE 5
271 BIT(1) | BIT(0))
279 #define LSM6DS0_MASK_FIFO_SRC_FSS (BIT(5) | BIT(4) | BIT(3) | \
280 BIT(2) | BIT(1) | BIT(0))
288 #define LSM6DS0_MASK_INT_GEN_CFG_G_ZHIE_G BIT(5)
289 #define LSM6DS0_SHIFT_INT_GEN_CFG_G_ZHIE_G 5
296 #define LSM6DS0_MASK_INT_GEN_CFG_G_XHIE_G BIT(1)
297 #define LSM6DS0_SHIFT_INT_GEN_CFG_G_XHIE_G 1
320 #define LSM6DS0_ACCEL_ENABLE_X_AXIS 1
326 #define LSM6DS0_ACCEL_ENABLE_Y_AXIS 1
332 #define LSM6DS0_ACCEL_ENABLE_Z_AXIS 1
338 #define LSM6DS0_GYRO_ENABLE_X_AXIS 1
344 #define LSM6DS0_GYRO_ENABLE_Y_AXIS 1
350 #define LSM6DS0_GYRO_ENABLE_Z_AXIS 1
375 #define LSM6DS0_DEFAULT_ACCEL_FULLSCALE 1
398 #define LSM6DS0_DEFAULT_ACCEL_SAMPLING_RATE 1
406 #define LSM6DS0_DEFAULT_ACCEL_SAMPLING_RATE 5
423 #define LSM6DS0_DEFAULT_GYRO_FULLSCALE 1
449 #define LSM6DS0_DEFAULT_GYRO_SAMPLING_RATE 1
457 #define LSM6DS0_DEFAULT_GYRO_SAMPLING_RATE 5