Lines Matching +full:0 +full:- +full:5

1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature
8  * SPDX-License-Identifier: Apache-2.0
18 #define LPS22HB_REG_WHO_AM_I                    0x0F
19 #define LPS22HB_VAL_WHO_AM_I                    0xB1
21 #define LPS22HB_REG_INTERRUPT_CFG               0x0B
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO     BIT(5)
27 #define LPS22HB_SHIFT_INTERRUPT_CFG_AUTOZERO    5
36 #define LPS22HB_MASK_INTERRUPT_CFG_PH_E         BIT(0)
37 #define LPS22HB_SHIFT_INTERRUPT_CFG_PH_E        0
39 #define LPS22HB_REG_THS_P_L                     0x0C
40 #define LPS22HB_REG_THS_P_H                     0x0D
42 #define LPS22HB_REG_CTRL_REG1                   0x10
43 #define LPS22HB_MASK_CTRL_REG1_ODR              (BIT(6) | BIT(5) | BIT(4))
51 #define LPS22HB_MASK_CTRL_REG1_SIM              BIT(0)
52 #define LPS22HB_SHIFT_CTRL_REG1_SIM             0
54 #define LPS22HB_REG_CTRL_REG2                   0x11
59 #define LPS22HB_MASK_CTRL_REG2_STOP_ON_FTH      BIT(5)
60 #define LPS22HB_SHIFT_CTRL_REG2_STOP_ON_FTH     5
67 #define LPS22HB_MASK_CTRL_REG2_ONE_SHOT         BIT(0)
68 #define LPS22HB_SHIFT_CTRL_REG2_ONE_SHOT        0
70 #define LPS22HB_REG_CTRL_REG3                   0x12
75 #define LPS22HB_MASK_CTRL_REG3_F_FSS5           BIT(5)
76 #define LPS22HB_SHIFT_CTRL_REG3_F_FFS5          5
83 #define LPS22HB_MASK_CTRL_REG3_INT_S            (BIT(1) | BIT(0))
84 #define LPS22HB_SHIFT_CTRL_REG_INT_S            0
86 #define LPS22HB_REG_FIFO_CTRL                   0x14
87 #define LPS22HB_MASK_FIFO_CTRL_F_MODE           (BIT(7) | BIT(6) | BIT(5))
88 #define LPS22HB_SHIFT_FIFO_CTRL_F_MODE          5
90 						 BIT(2) | BIT(1) | BIT(0))
91 #define LPS22HB_SHIFT_FIFO_CTRL_WTM             0
93 #define LPS22HB_REG_REF_P_XL                    0x15
94 #define LPS22HB_REG_REF_P_L                     0x16
95 #define LPS22HB_REG_REF_P_H                     0x17
97 #define LPS22HB_REG_RPDS_L                      0x18
98 #define LPS22HB_REG_RPDS_H                      0x19
100 #define LPS22HB_REG_RES_CONF                    0x1A
101 #define LPS22HB_MASK_RES_CONF_LC_EN             BIT(0)
102 #define LPS22HB_SHIFT_RES_CONF_LC_EN            0
104 #define LPS22HB_REG_INT_SOURCE                  0x25
109 #define LPS22HB_MASK_INT_SOURCE_PH              BIT(0)
110 #define LPS22HB_SHIFT_INT_SOURCE_PH             0
112 #define LPS22HB_REG_FIFO_STATUS                 0x26
117 #define LPS22HB_MASK_FIFO_STATUS_EMPTY_FIFO     BIT(5)
118 #define LPS22HB_SHIFT_FIFO_STATUS_EMPTY_FIFO    5
120 						 BIT(1) | BIT(0))
121 #define LPS22HB_SHIFT_FIFO_STATUS_FSS           0
123 #define LPS22HB_REG_STATUS                      0x27
124 #define LPS22HB_MASK_STATUS_P_OR                BIT(5)
125 #define LPS22HB_SHIFT_STATUS_P_OR               5
130 #define LPS22HB_MASK_STATUS_T_DA                BIT(0)
131 #define LPS22HB_SHIFT_STATUS_T_DA               0
133 #define LPS22HB_REG_PRESS_OUT_XL                0x28
134 #define LPS22HB_REG_PRESS_OUT_L                 0x29
135 #define LPS22HB_REG_PRESS_OUT_H                 0x2A
137 #define LPS22HB_REG_TEMP_OUT_L                  0x2B
138 #define LPS22HB_REG_TEMP_OUT_H                  0x2C
140 #define LPS22HB_REG_LPFP_RES                    0x33
152 	#define LPS22HB_DEFAULT_SAMPLING_RATE      5