Lines Matching +full:0 +full:x04

15 #define TSL2540_REG_ATIME    0x81
16 #define TSL2540_REG_WTIME    0x83
17 #define TSL2540_REG_AILT_LOW 0x84
18 #define TSL2540_REG_AILT_HI  0x85
19 #define TSL2540_REG_AIHT_LOW 0x86
20 #define TSL2540_REG_AIHT_HI  0x87
21 #define TSL2540_REG_PERS     0x8c
22 #define TSL2540_REG_CFG_0    0x8d
23 #define TSL2540_REG_CFG_1    0x90
24 #define TSL2540_REG_REVID    0x91
25 #define TSL2540_REG_ID	     0x92
26 #define TSL2540_REG_STATUS   0x93
27 #define TSL2540_REG_VIS_LOW  0x94
28 #define TSL2540_REG_VIS_HI   0x95
29 #define TSL2540_REG_IR_LOW   0x96
30 #define TSL2540_REG_IR_HI    0x97
31 #define TSL2540_REG_REVID2   0x9E
32 #define TSL2540_REG_CFG_2    0x9f
41 #define TSL2540_CFG1_G1_2 0x00
42 #define TSL2540_CFG1_G1	  0x00
43 #define TSL2540_CFG1_G4	  0x01
44 #define TSL2540_CFG1_G16  0x02
45 #define TSL2540_CFG1_G64  0x03
46 #define TSL2540_CFG1_G128 0x03
48 #define TSL2540_CFG2_G1_2 0x00
49 #define TSL2540_CFG2_G1	  0x04
50 #define TSL2540_CFG2_G4	  0x04
51 #define TSL2540_CFG2_G16  0x04
52 #define TSL2540_CFG2_G64  0x04
53 #define TSL2540_CFG2_G128 0x14
55 /* ENABLE(0x80: 0x00): Reserved:7:4 | WEN:3 | Reserved:2 | AEN:1 | PON:0 */
56 #define TSL2540_ENABLE_ADDR 0x80
57 #define TSL2540_ENABLE_MASK (BIT(3) | BIT(1) | BIT(0))
58 #define TSL2540_ENABLE_CONF (BIT(3) | BIT(1) | BIT(0))
59 #define TSL2540_ENABLE_AEN_PON (BIT(1) | BIT(0))
60 #define TSL2540_ENABLE_DISABLE (0)
62 /* CRG3(0xAB: 0x0C):  INT_READ_CLEAR:7 | Reserved:6:5 | SAI:4 | Reserved:3:0 */
63 #define TSL2540_CFG3_ADDR 0xAB
66 #define TSL2540_CFG3_DFLT (0)
68 /* INTENAB(0xDD: 0x00): ASIEN:7 | Reserved:6:5 | AIEN:4 | Reserved:3:0 */
69 #define TSL2540_INTENAB_ADDR 0xDD
73 #define TSL2540_INT_EN_AEN 0x90