Lines Matching +full:adxl362 +full:- +full:trigger
4 * SPDX-License-Identifier: Apache-2.0
12 LOG_MODULE_DECLARE(ADXL362, CONFIG_SENSOR_LOG_LEVEL);
23 gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE); in adxl367_sqe_done()
29 const struct adxl367_dev_config *cfg = dev->config; in adxl367_irq_en_cb()
31 gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE); in adxl367_irq_en_cb()
36 struct adxl367_data *data = dev->data; in adxl367_fifo_flush_rtio()
37 uint8_t pow_reg = data->pwr_reg; in adxl367_fifo_flush_rtio()
42 struct rtio_sqe *sqe = rtio_sqe_acquire(data->rtio_ctx); in adxl367_fifo_flush_rtio()
45 rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w, 3, NULL); in adxl367_fifo_flush_rtio()
47 sqe = rtio_sqe_acquire(data->rtio_ctx); in adxl367_fifo_flush_rtio()
51 rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w2, 3, NULL); in adxl367_fifo_flush_rtio()
53 sqe = rtio_sqe_acquire(data->rtio_ctx); in adxl367_fifo_flush_rtio()
55 FIELD_PREP(ADXL367_FIFO_CONTROL_FIFO_MODE_MSK, data->fifo_config.fifo_mode)}; in adxl367_fifo_flush_rtio()
57 rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w3, 3, NULL); in adxl367_fifo_flush_rtio()
59 pow_reg = data->pwr_reg; in adxl367_fifo_flush_rtio()
64 sqe = rtio_sqe_acquire(data->rtio_ctx); in adxl367_fifo_flush_rtio()
65 struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx); in adxl367_fifo_flush_rtio()
68 rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w4, 3, NULL); in adxl367_fifo_flush_rtio()
69 sqe->flags |= RTIO_SQE_CHAINED; in adxl367_fifo_flush_rtio()
71 rtio_submit(data->rtio_ctx, 0); in adxl367_fifo_flush_rtio()
77 (const struct sensor_read_config *)iodev_sqe->sqe.iodev->data; in adxl367_submit_stream()
78 struct adxl367_data *data = (struct adxl367_data *)dev->data; in adxl367_submit_stream()
79 const struct adxl367_dev_config *cfg_367 = dev->config; in adxl367_submit_stream()
85 int rc = gpio_pin_interrupt_configure_dt(&cfg_367->interrupt, in adxl367_submit_stream()
91 for (size_t i = 0; i < cfg->count; i++) { in adxl367_submit_stream()
92 if (cfg->triggers[i].trigger == SENSOR_TRIG_FIFO_WATERMARK) { in adxl367_submit_stream()
98 if (cfg->triggers[i].trigger == SENSOR_TRIG_FIFO_FULL) { in adxl367_submit_stream()
105 if (data->fifo_wmark_irq && (fifo_wmark_irq == 0)) { in adxl367_submit_stream()
109 if (data->fifo_full_irq && (fifo_full_irq == 0)) { in adxl367_submit_stream()
114 if ((fifo_wmark_irq != data->fifo_wmark_irq) || (fifo_full_irq != data->fifo_full_irq)) { in adxl367_submit_stream()
115 data->fifo_wmark_irq = fifo_wmark_irq; in adxl367_submit_stream()
116 data->fifo_full_irq = fifo_full_irq; in adxl367_submit_stream()
118 rc = data->hw_tf->write_reg_mask(dev, ADXL367_INTMAP1_LOWER, int_mask, int_value); in adxl367_submit_stream()
124 enum adxl367_fifo_mode current_fifo_mode = data->fifo_config.fifo_mode; in adxl367_submit_stream()
133 adxl367_fifo_setup(dev, ADXL367_FIFO_DISABLED, data->fifo_config.fifo_format, in adxl367_submit_stream()
134 data->fifo_config.fifo_read_mode, data->fifo_config.fifo_samples); in adxl367_submit_stream()
136 adxl367_fifo_setup(dev, current_fifo_mode, data->fifo_config.fifo_format, in adxl367_submit_stream()
137 data->fifo_config.fifo_read_mode, data->fifo_config.fifo_samples); in adxl367_submit_stream()
139 adxl367_set_op_mode(dev, cfg_367->op_mode); in adxl367_submit_stream()
142 rc = gpio_pin_interrupt_configure_dt(&cfg_367->interrupt, in adxl367_submit_stream()
148 data->sqe = iodev_sqe; in adxl367_submit_stream()
154 const struct adxl367_dev_config *cfg = (const struct adxl367_dev_config *)dev->config; in adxl367_fifo_read_cb()
155 struct rtio_iodev_sqe *iodev_sqe = sqe->userdata; in adxl367_fifo_read_cb()
164 switch (data->fifo_config.fifo_format) { in adxl367_get_numb_of_samp_in_pkt()
196 struct adxl367_data *data = (struct adxl367_data *)dev->data; in adxl367_process_fifo_samples_cb()
197 const struct adxl367_dev_config *cfg = (const struct adxl367_dev_config *)dev->config; in adxl367_process_fifo_samples_cb()
198 struct rtio_iodev_sqe *current_sqe = data->sqe; in adxl367_process_fifo_samples_cb()
199 uint16_t fifo_samples = ((data->fifo_ent[0]) | ((data->fifo_ent[1] & 0x3) << 8)); in adxl367_process_fifo_samples_cb()
205 switch (data->fifo_config.fifo_read_mode) { in adxl367_process_fifo_samples_cb()
217 fifo_bits -= sample_numb * 12; in adxl367_process_fifo_samples_cb()
228 adxl367_sqe_done(cfg, current_sqe, -1); in adxl367_process_fifo_samples_cb()
245 data->sqe = NULL; in adxl367_process_fifo_samples_cb()
250 gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE); in adxl367_process_fifo_samples_cb()
262 adxl367_sqe_done(cfg, current_sqe, -ENOMEM); in adxl367_process_fifo_samples_cb()
272 hdr->is_fifo = 1; in adxl367_process_fifo_samples_cb()
273 hdr->timestamp = data->timestamp; in adxl367_process_fifo_samples_cb()
274 hdr->int_status = data->status; in adxl367_process_fifo_samples_cb()
275 hdr->accel_odr = data->odr; in adxl367_process_fifo_samples_cb()
276 hdr->range = data->range; in adxl367_process_fifo_samples_cb()
277 hdr->fifo_read_mode = data->fifo_config.fifo_read_mode; in adxl367_process_fifo_samples_cb()
279 if (data->fifo_config.fifo_read_mode == ADXL367_12B) { in adxl367_process_fifo_samples_cb()
280 hdr->packet_size = sample_numb; in adxl367_process_fifo_samples_cb()
282 hdr->packet_size = packet_size; in adxl367_process_fifo_samples_cb()
285 if ((data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_X) || in adxl367_process_fifo_samples_cb()
286 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XT) || in adxl367_process_fifo_samples_cb()
287 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XA) || in adxl367_process_fifo_samples_cb()
288 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZ) || in adxl367_process_fifo_samples_cb()
289 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZA) || in adxl367_process_fifo_samples_cb()
290 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZT)) { in adxl367_process_fifo_samples_cb()
291 hdr->has_x = 1; in adxl367_process_fifo_samples_cb()
294 if ((data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_Y) || in adxl367_process_fifo_samples_cb()
295 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_YT) || in adxl367_process_fifo_samples_cb()
296 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_YA) || in adxl367_process_fifo_samples_cb()
297 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZ) || in adxl367_process_fifo_samples_cb()
298 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZA) || in adxl367_process_fifo_samples_cb()
299 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZT)) { in adxl367_process_fifo_samples_cb()
300 hdr->has_y = 1; in adxl367_process_fifo_samples_cb()
303 if ((data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_Z) || in adxl367_process_fifo_samples_cb()
304 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_ZT) || in adxl367_process_fifo_samples_cb()
305 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_ZA) || in adxl367_process_fifo_samples_cb()
306 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZ) || in adxl367_process_fifo_samples_cb()
307 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZA) || in adxl367_process_fifo_samples_cb()
308 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZT)) { in adxl367_process_fifo_samples_cb()
309 hdr->has_z = 1; in adxl367_process_fifo_samples_cb()
312 if ((data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XT) || in adxl367_process_fifo_samples_cb()
313 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_YT) || in adxl367_process_fifo_samples_cb()
314 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_ZT) || in adxl367_process_fifo_samples_cb()
315 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZT)) { in adxl367_process_fifo_samples_cb()
316 hdr->has_tmp = 1; in adxl367_process_fifo_samples_cb()
319 if ((data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XA) || in adxl367_process_fifo_samples_cb()
320 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_YA) || in adxl367_process_fifo_samples_cb()
321 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_ZA) || in adxl367_process_fifo_samples_cb()
322 (data->fifo_config.fifo_format == ADXL367_FIFO_FORMAT_XYZA)) { in adxl367_process_fifo_samples_cb()
323 hdr->has_adc = 1; in adxl367_process_fifo_samples_cb()
328 buf_avail -= sizeof(*hdr); in adxl367_process_fifo_samples_cb()
332 if (data->fifo_config.fifo_read_mode == ADXL367_12B) { in adxl367_process_fifo_samples_cb()
343 read_len_bits -= sample_numb * 12; in adxl367_process_fifo_samples_cb()
354 adxl367_sqe_done(cfg, current_sqe, -ENOMEM); in adxl367_process_fifo_samples_cb()
364 ((struct adxl367_fifo_data *)buf)->fifo_byte_count = read_len; in adxl367_process_fifo_samples_cb()
375 cqe = rtio_cqe_consume(data->rtio_ctx); in adxl367_process_fifo_samples_cb()
377 if ((cqe->result < 0 && res == 0)) { in adxl367_process_fifo_samples_cb()
378 LOG_ERR("Bus error: %d", cqe->result); in adxl367_process_fifo_samples_cb()
379 res = cqe->result; in adxl367_process_fifo_samples_cb()
381 rtio_cqe_release(data->rtio_ctx, cqe); in adxl367_process_fifo_samples_cb()
394 struct rtio_sqe *write_fifo_addr = rtio_sqe_acquire(data->rtio_ctx); in adxl367_process_fifo_samples_cb()
395 struct rtio_sqe *read_fifo_data = rtio_sqe_acquire(data->rtio_ctx); in adxl367_process_fifo_samples_cb()
396 struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx); in adxl367_process_fifo_samples_cb()
399 rtio_sqe_prep_tiny_write(write_fifo_addr, data->iodev, RTIO_PRIO_NORM, ®_addr, 1, NULL); in adxl367_process_fifo_samples_cb()
400 write_fifo_addr->flags = RTIO_SQE_TRANSACTION; in adxl367_process_fifo_samples_cb()
401 rtio_sqe_prep_read(read_fifo_data, data->iodev, RTIO_PRIO_NORM, read_buf, read_len, in adxl367_process_fifo_samples_cb()
403 read_fifo_data->flags = RTIO_SQE_CHAINED; in adxl367_process_fifo_samples_cb()
406 rtio_submit(data->rtio_ctx, 0); in adxl367_process_fifo_samples_cb()
412 struct adxl367_data *data = (struct adxl367_data *) dev->data; in adxl367_process_status_cb()
413 const struct adxl367_dev_config *cfg = (const struct adxl367_dev_config *) dev->config; in adxl367_process_status_cb()
414 struct rtio_iodev_sqe *current_sqe = data->sqe; in adxl367_process_status_cb()
416 uint8_t status = data->status; in adxl367_process_status_cb()
418 __ASSERT(data->sqe != NULL, "%s data->sqe = NULL", __func__); in adxl367_process_status_cb()
420 read_config = (struct sensor_read_config *)data->sqe->sqe.iodev->data; in adxl367_process_status_cb()
424 __ASSERT(read_config->is_streaming != false, in adxl367_process_status_cb()
425 "%s read_config->is_streaming = false", __func__); in adxl367_process_status_cb()
427 gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_DISABLE); in adxl367_process_status_cb()
432 for (int i = 0; i < read_config->count; ++i) { in adxl367_process_status_cb()
433 if (read_config->triggers[i].trigger == SENSOR_TRIG_FIFO_WATERMARK) { in adxl367_process_status_cb()
434 fifo_wmark_cfg = &read_config->triggers[i]; in adxl367_process_status_cb()
438 if (read_config->triggers[i].trigger == SENSOR_TRIG_FIFO_FULL) { in adxl367_process_status_cb()
439 fifo_full_cfg = &read_config->triggers[i]; in adxl367_process_status_cb()
456 gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE); in adxl367_process_status_cb()
465 cqe = rtio_cqe_consume(data->rtio_ctx); in adxl367_process_status_cb()
467 if ((cqe->result < 0 && res == 0)) { in adxl367_process_status_cb()
468 LOG_ERR("Bus error: %d", cqe->result); in adxl367_process_status_cb()
469 res = cqe->result; in adxl367_process_status_cb()
471 rtio_cqe_release(data->rtio_ctx, cqe); in adxl367_process_status_cb()
484 data_opt = fifo_wmark_cfg->opt; in adxl367_process_status_cb()
486 data_opt = fifo_full_cfg->opt; in adxl367_process_status_cb()
488 data_opt = MIN(fifo_wmark_cfg->opt, fifo_full_cfg->opt); in adxl367_process_status_cb()
496 data->sqe = NULL; in adxl367_process_status_cb()
499 adxl367_sqe_done(cfg, current_sqe, -ENOMEM); in adxl367_process_status_cb()
506 rx_data->is_fifo = 1; in adxl367_process_status_cb()
507 rx_data->timestamp = data->timestamp; in adxl367_process_status_cb()
508 rx_data->int_status = status; in adxl367_process_status_cb()
509 rx_data->fifo_byte_count = 0; in adxl367_process_status_cb()
521 struct rtio_sqe *write_fifo_addr = rtio_sqe_acquire(data->rtio_ctx); in adxl367_process_status_cb()
522 struct rtio_sqe *read_fifo_data = rtio_sqe_acquire(data->rtio_ctx); in adxl367_process_status_cb()
523 struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx); in adxl367_process_status_cb()
526 rtio_sqe_prep_tiny_write(write_fifo_addr, data->iodev, RTIO_PRIO_NORM, reg, 2, NULL); in adxl367_process_status_cb()
527 write_fifo_addr->flags = RTIO_SQE_TRANSACTION; in adxl367_process_status_cb()
528 rtio_sqe_prep_read(read_fifo_data, data->iodev, RTIO_PRIO_NORM, data->fifo_ent, 2, in adxl367_process_status_cb()
530 read_fifo_data->flags = RTIO_SQE_CHAINED; in adxl367_process_status_cb()
534 rtio_submit(data->rtio_ctx, 0); in adxl367_process_status_cb()
539 struct adxl367_data *data = (struct adxl367_data *) dev->data; in adxl367_stream_irq_handler()
541 if (data->sqe == NULL) { in adxl367_stream_irq_handler()
545 data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks()); in adxl367_stream_irq_handler()
547 struct rtio_sqe *write_status_addr = rtio_sqe_acquire(data->rtio_ctx); in adxl367_stream_irq_handler()
548 struct rtio_sqe *read_status_reg = rtio_sqe_acquire(data->rtio_ctx); in adxl367_stream_irq_handler()
549 struct rtio_sqe *check_status_reg = rtio_sqe_acquire(data->rtio_ctx); in adxl367_stream_irq_handler()
552 rtio_sqe_prep_tiny_write(write_status_addr, data->iodev, RTIO_PRIO_NORM, reg, 2, NULL); in adxl367_stream_irq_handler()
553 write_status_addr->flags = RTIO_SQE_TRANSACTION; in adxl367_stream_irq_handler()
554 rtio_sqe_prep_read(read_status_reg, data->iodev, RTIO_PRIO_NORM, &data->status, 1, NULL); in adxl367_stream_irq_handler()
555 read_status_reg->flags = RTIO_SQE_CHAINED; in adxl367_stream_irq_handler()
557 rtio_submit(data->rtio_ctx, 0); in adxl367_stream_irq_handler()