Lines Matching +full:settle +full:- +full:time
4 * SPDX-License-Identifier: Apache-2.0
29 * @param dev - The device structure.
30 * @param th - Structure holding the activity threshold information:
39 struct adxl367_data *data = dev->data; in adxl367_setup_activity_detection()
43 ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL, in adxl367_setup_activity_detection()
46 FIELD_PREP(ADXL367_ACT_INACT_CTL_ACT_EN_MSK, th->enable) | in adxl367_setup_activity_detection()
48 th->referenced)); in adxl367_setup_activity_detection()
53 ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_H, ADXL367_THRESH_H_MSK, in adxl367_setup_activity_detection()
54 FIELD_PREP(ADXL367_THRESH_H_MSK, th->value >> 6)); in adxl367_setup_activity_detection()
59 return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_L, ADXL367_THRESH_L_MSK, in adxl367_setup_activity_detection()
60 FIELD_PREP(ADXL367_THRESH_L_MSK, th->value & 0x3F)); in adxl367_setup_activity_detection()
66 * @param dev - The device structure.
67 * @param th - Structure holding the inactivity threshold information:
77 struct adxl367_data *data = dev->data; in adxl367_setup_inactivity_detection()
80 ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL, in adxl367_setup_inactivity_detection()
84 th->enable) | in adxl367_setup_inactivity_detection()
86 th->referenced)); in adxl367_setup_inactivity_detection()
91 ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_H, ADXL367_THRESH_H_MSK, in adxl367_setup_inactivity_detection()
92 FIELD_PREP(ADXL367_THRESH_H_MSK, th->value >> 6)); in adxl367_setup_inactivity_detection()
97 return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_L, ADXL367_THRESH_L_MSK, in adxl367_setup_inactivity_detection()
98 FIELD_PREP(ADXL367_THRESH_L_MSK, th->value & 0x3F)); in adxl367_setup_inactivity_detection()
104 * @param dev - The device structure.
105 * @param op_mode - Mode of operation.
119 struct adxl367_data *data = dev->data; in adxl367_set_op_mode()
122 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL, in adxl367_set_op_mode()
130 /* Wait 100 ms to allow the acceleration outputs to settle */ in adxl367_set_op_mode()
135 data->pwr_reg &= ~ADXL367_POWER_CTL_MEASURE_MSK; in adxl367_set_op_mode()
136 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_MEASURE_MSK, op_mode); in adxl367_set_op_mode()
144 * wake-up mode automatically upon detection of inactivity.
146 * @param dev - The device structure.
147 * @param enable - Accepted values: true
155 struct adxl367_data *data = dev->data; in adxl367_set_autosleep()
157 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL, in adxl367_set_autosleep()
163 data->pwr_reg &= ~ADXL367_POWER_CTL_AUTOSLEEP_MSK; in adxl367_set_autosleep()
164 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_AUTOSLEEP_MSK, enable); in adxl367_set_autosleep()
174 * @param dev - The device structure.
175 * @param enable - Accepted values: true
183 struct adxl367_data *data = dev->data; in adxl367_set_low_noise()
185 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL, in adxl367_set_low_noise()
191 data->pwr_reg &= ~ADXL367_POWER_CTL_NOISE_MSK; in adxl367_set_low_noise()
192 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_NOISE_MSK, enable); in adxl367_set_low_noise()
202 * @param dev - The device structure.
203 * @param mode - Mode of operation.
213 struct adxl367_data *data = dev->data; in adxl367_set_act_proc_mode()
215 return data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL, in adxl367_set_act_proc_mode()
223 * @param dev - The device structure.
224 * @param odr - Output Data Rate option.
235 struct adxl367_data *data = dev->data; in adxl367_set_output_rate()
238 ret = data->hw_tf->write_reg_mask(dev, in adxl367_set_output_rate()
245 data->odr = odr; in adxl367_set_output_rate()
255 * @param dev - The device structure.
256 * @param range - Range option.
257 * Accepted values: ADXL367_2G_RANGE, +/- 2g
258 * ADXL367_4G_RANGE, +/- 4g
259 * ADXL367_8G_RANGE +/- 8g
265 struct adxl367_data *data = dev->data; in adxl367_set_range()
268 ret = data->hw_tf->write_reg_mask(dev, in adxl367_set_range()
275 data->range = range; in adxl367_set_range()
285 * @param dev - The device structure.
286 * @param time - The value set in this register.
290 static int adxl367_set_activity_time(const struct device *dev, uint8_t time) in adxl367_set_activity_time() argument
292 struct adxl367_data *data = dev->data; in adxl367_set_activity_time()
294 return data->hw_tf->write_reg(dev, ADXL367_TIME_ACT, time); in adxl367_set_activity_time()
299 * @param dev - The device structure.
300 * @param time - is the 16-bit value set by the TIME_INACT_L register
305 uint16_t time) in adxl367_set_inactivity_time() argument
308 struct adxl367_data *data = dev->data; in adxl367_set_inactivity_time()
310 ret = data->hw_tf->write_reg(dev, ADXL367_TIME_INACT_H, time >> 8); in adxl367_set_inactivity_time()
315 return data->hw_tf->write_reg(dev, ADXL367_TIME_INACT_L, time & 0xFF); in adxl367_set_inactivity_time()
321 * @param dev - The device structure.
328 struct adxl367_data *data = dev->data; in adxl367_self_test()
329 const struct adxl367_dev_config *cfg = dev->config; in adxl367_self_test()
336 switch (cfg->odr) { in adxl367_self_test()
356 return -EINVAL; in adxl367_self_test()
364 ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, ADXL367_SELF_TEST_ST_MSK, in adxl367_self_test()
373 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_X_DATA_H, read_val, 2); in adxl367_self_test()
385 ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, in adxl367_self_test()
395 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_X_DATA_H, read_val, 2); in adxl367_self_test()
412 ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, ADXL367_SELF_TEST_ST_FORCE_MSK | in adxl367_self_test()
420 dif = x_axis_2 - x_axis_1; in adxl367_self_test()
421 min = ADXL367_SELF_TEST_MIN * adxl367_scale_mul[data->range]; in adxl367_self_test()
422 max = ADXL367_SELF_TEST_MAX * adxl367_scale_mul[data->range]; in adxl367_self_test()
425 LOG_INF("ADXL367 passed self-test\n"); in adxl367_self_test()
428 LOG_ERR("ADXL367 failed self-test\n"); in adxl367_self_test()
429 ret = -EINVAL; in adxl367_self_test()
438 * @param dev - The device structure.
439 * @param enable - 1 - ENABLE
440 * 2 - DISABLE
446 struct adxl367_data *data = dev->data; in adxl367_temp_read_en()
448 return data->hw_tf->write_reg_mask(dev, in adxl367_temp_read_en()
457 * @param dev - The device structure.
458 * @param sets_nb - Sample sets number. For example, if ADXL367_FIFO_FORMAT_XYZ
466 struct adxl367_data *data = dev->data; in adxl367_set_fifo_sample_sets_nb()
471 ret = data->hw_tf->write_reg_mask(dev, ADXL367_FIFO_CONTROL, in adxl367_set_fifo_sample_sets_nb()
480 return data->hw_tf->write_reg(dev, ADXL367_FIFO_SAMPLES, sets_nb & 0xFF); in adxl367_set_fifo_sample_sets_nb()
486 * @param dev - The device structure.
487 * @param mode - FIFO mode.
498 struct adxl367_data *data = dev->data; in adxl367_set_fifo_mode()
500 return data->hw_tf->write_reg_mask(dev, in adxl367_set_fifo_mode()
509 * @param dev - The device structure.
510 * @param read_mode - FIFO read mode.
521 struct adxl367_data *data = dev->data; in adxl367_set_fifo_read_mode()
523 return data->hw_tf->write_reg_mask(dev, ADXL367_ADC_CTL, in adxl367_set_fifo_read_mode()
531 * @param dev - The device structure.
532 * @param format - FIFO format.
552 struct adxl367_data *data = dev->data; in adxl367_set_fifo_format()
554 ret = data->hw_tf->write_reg_mask(dev, in adxl367_set_fifo_format()
584 return -EINVAL; in adxl367_set_fifo_format()
594 * @param dev - The device structure.
595 * @param mode - FIFO mode selection.
600 * @param format - FIFO format selection.
613 * @param read_mode - FIFO read mode.
618 * @param sets_nb - Specifies the number of samples sets to store in the FIFO.
651 struct adxl367_data *data = (struct adxl367_data *)dev->data; in adxl367_fifo_setup()
653 data->fifo_config.fifo_mode = mode; in adxl367_fifo_setup()
654 data->fifo_config.fifo_format = format; in adxl367_fifo_setup()
655 data->fifo_config.fifo_samples = sets_nb; in adxl367_fifo_setup()
656 data->fifo_config.fifo_read_mode = read_mode; in adxl367_fifo_setup()
665 * @param dev - The device structure.
672 struct adxl367_data *data = dev->data; in adxl367_reset()
680 ret = data->hw_tf->write_reg(dev, ADXL367_SOFT_RESET, ADXL367_RESET_CODE); in adxl367_reset()
693 * @brief Reads the 3-axis raw data from the accelerometer.
695 * @param dev - The device structure.
696 * @param accel_data - store the XYZ axis accelerometer data.
706 struct adxl367_data *data = dev->data; in adxl367_get_accel_data()
709 ret = data->hw_tf->read_reg(dev, ADXL367_STATUS, ®_data); in adxl367_get_accel_data()
719 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_X_DATA_H, xyz_values, 6); in adxl367_get_accel_data()
725 accel_data->x = ((int16_t)xyz_values[0] << 6) + (xyz_values[1] >> 2); in adxl367_get_accel_data()
726 accel_data->y = ((int16_t)xyz_values[2] << 6) + (xyz_values[3] >> 2); in adxl367_get_accel_data()
727 accel_data->z = ((int16_t)xyz_values[4] << 6) + (xyz_values[5] >> 2); in adxl367_get_accel_data()
730 if ((accel_data->x & BIT(13)) != 0) { in adxl367_get_accel_data()
731 accel_data->x |= GENMASK(15, 14); in adxl367_get_accel_data()
734 if ((accel_data->y & BIT(13)) != 0) { in adxl367_get_accel_data()
735 accel_data->y |= GENMASK(15, 14); in adxl367_get_accel_data()
738 if ((accel_data->z & BIT(13)) != 0) { in adxl367_get_accel_data()
739 accel_data->z |= GENMASK(15, 14); in adxl367_get_accel_data()
749 * @param dev - The device structure.
750 * @param raw_temp - Raw value of temperature.
759 struct adxl367_data *data = dev->data; in adxl367_get_temp_data()
762 ret = data->hw_tf->read_reg(dev, ADXL367_STATUS, ®_data); in adxl367_get_temp_data()
772 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_TEMP_H, temp, 2); in adxl367_get_temp_data()
791 const struct adxl367_dev_config *cfg = dev->config; in adxl367_attr_set_thresh()
795 int64_t micro_ms2 = val->val1 * 1000000LL + val->val2; in adxl367_attr_set_thresh()
802 threshold.enable = cfg->activity_th.enable; in adxl367_attr_set_thresh()
803 threshold.referenced = cfg->activity_th.referenced; in adxl367_attr_set_thresh()
818 return -ENOTSUP; in adxl367_attr_set_thresh()
829 switch (val->val1) { in adxl367_attr_set_odr()
850 return -EINVAL; in adxl367_attr_set_odr()
868 return -ENOTSUP; in adxl367_attr_set()
875 struct adxl367_data *data = dev->data; in adxl367_sample_fetch()
878 ret = adxl367_get_accel_data(dev, &data->sample); in adxl367_sample_fetch()
883 return adxl367_get_temp_data(dev, &data->temp_val); in adxl367_sample_fetch()
896 val->val1 = micro_ms2 / 1000000; in adxl367_accel_convert()
897 val->val2 = micro_ms2 % 1000000; in adxl367_accel_convert()
906 int64_t temp_data = (value - ADXL367_TEMP_25C); in adxl367_temp_convert()
908 val->val1 = temp_data / 54 /*temp sensitivity LSB/C*/ + 25/*bias test conditions*/; in adxl367_temp_convert()
909 val->val2 = temp_data % 54 * 10000; in adxl367_temp_convert()
916 struct adxl367_data *data = dev->data; in adxl367_channel_get()
920 adxl367_accel_convert(val, data->sample.x, data->range); in adxl367_channel_get()
923 adxl367_accel_convert(val, data->sample.y, data->range); in adxl367_channel_get()
926 adxl367_accel_convert(val, data->sample.z, data->range); in adxl367_channel_get()
929 adxl367_accel_convert(val++, data->sample.x, data->range); in adxl367_channel_get()
930 adxl367_accel_convert(val++, data->sample.y, data->range); in adxl367_channel_get()
931 adxl367_accel_convert(val, data->sample.z, data->range); in adxl367_channel_get()
934 adxl367_temp_convert(val, data->temp_val); in adxl367_channel_get()
937 return -ENOTSUP; in adxl367_channel_get()
958 const struct adxl367_dev_config *cfg = dev->config; in adxl367_probe()
959 struct adxl367_data *data = dev->data; in adxl367_probe()
968 ret = data->hw_tf->read_reg(dev, ADXL367_DEVID, &dev_id); in adxl367_probe()
972 ret = data->hw_tf->read_reg(dev, ADXL367_PART_ID, &part_id); in adxl367_probe()
979 return -ENODEV; in adxl367_probe()
982 data->range = cfg->range; in adxl367_probe()
985 data->act_proc_mode = ADXL367_LINKED; in adxl367_probe()
987 data->act_proc_mode = ADXL367_LOOPED; in adxl367_probe()
995 ret = adxl367_temp_read_en(dev, cfg->temp_en); in adxl367_probe()
1000 ret = adxl367_set_autosleep(dev, cfg->autosleep); in adxl367_probe()
1005 ret = adxl367_set_low_noise(dev, cfg->low_noise); in adxl367_probe()
1010 ret = adxl367_setup_activity_detection(dev, &cfg->activity_th); in adxl367_probe()
1015 ret = adxl367_setup_inactivity_detection(dev, &cfg->inactivity_th); in adxl367_probe()
1020 ret = adxl367_set_activity_time(dev, cfg->activity_time); in adxl367_probe()
1025 ret = adxl367_set_inactivity_time(dev, cfg->inactivity_time); in adxl367_probe()
1030 ret = adxl367_set_output_rate(dev, cfg->odr); in adxl367_probe()
1035 ret = adxl367_fifo_setup(dev, cfg->fifo_config.fifo_mode, in adxl367_probe()
1036 cfg->fifo_config.fifo_format, in adxl367_probe()
1037 cfg->fifo_config.fifo_read_mode, in adxl367_probe()
1038 cfg->fifo_config.fifo_samples); in adxl367_probe()
1047 return -EIO; in adxl367_probe()
1051 ret = adxl367_set_op_mode(dev, cfg->op_mode); in adxl367_probe()
1056 ret = adxl367_set_range(dev, data->range); in adxl367_probe()
1061 return adxl367_set_act_proc_mode(dev, data->act_proc_mode); in adxl367_probe()
1067 const struct adxl367_dev_config *cfg = dev->config; in adxl367_init()
1069 ret = cfg->bus_init(dev); in adxl367_init()
1174 * bus-specific macro at preprocessor time.