Lines Matching +full:3 +full:x
64 #define ADXL362_STATUS_FIFO_OVERRUN (1 << 3)
70 #define ADXL362_ACT_INACT_CTL_LINKLOOP(x) (((x) & 0x3) << 4) argument
71 #define ADXL362_ACT_INACT_CTL_INACT_REF (1 << 3)
76 /* ADXL362_ACT_INACT_CTL_LINKLOOP(x) options */
79 #define ADXL362_MODE_LOOP 3
82 #define ADXL362_FIFO_CTL_AH (1 << 3)
84 #define ADXL362_FIFO_CTL_FIFO_MODE(x) (((x) & 0x3) << 0) argument
86 /* ADXL362_FIFO_CTL_FIFO_MODE(x) options */
90 #define ADXL362_FIFO_TRIGGERED 3
97 #define ADXL362_INTMAP1_FIFO_OVERRUN (1 << 3)
107 #define ADXL362_INTMAP2_FIFO_OVERRUN (1 << 3)
113 #define ADXL362_FILTER_CTL_RANGE(x) (((x) & 0x3) << 6) argument
116 #define ADXL362_FILTER_CTL_EXT_SAMPLE (1 << 3)
117 #define ADXL362_FILTER_CTL_ODR(x) (((x) & 0x7) << 0) argument
119 /* ADXL362_FILTER_CTL_RANGE(x) options */
124 /* ADXL362_FILTER_CTL_ODR(x) options */
128 #define ADXL362_ODR_100_HZ 3 /* 100 Hz */
135 #define ADXL362_POWER_CTL_LOW_NOISE(x) (((x) & 0x3) << 4) argument
136 #define ADXL362_POWER_CTL_WAKEUP (1 << 3)
138 #define ADXL362_POWER_CTL_MEASURE(x) (((x) & 0x3) << 0) argument
140 /* ADXL362_POWER_CTL_LOW_NOISE(x) options */
145 /* ADXL362_POWER_CTL_MEASURE(x) options */
161 #define ADXL362_STATUS_CHECK_DATA_READY(x) (((x) >> 0) & 0x1) argument
162 #define ADXL362_STATUS_CHECK_INACT(x) (((x) >> 5) & 0x1) argument
163 #define ADXL362_STATUS_CHECK_ACTIVITY(x) (((x) >> 4) & 0x1) argument
164 #define ADXL362_STATUS_CHECK_FIFO_OVR(x) (((x) >> 3) & 0x1) argument
165 #define ADXL362_STATUS_CHECK_FIFO_WTR(x) (((x) >> 2) & 0x1) argument
178 #define ADXL362_FIFO_HDR_CHECK_ACCEL_X(x) ((((x) & 0xC000) >> 14) == 0x00) argument
179 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Y(x) ((((x) & 0xC000) >> 14) == 0x01) argument
180 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Z(x) ((((x) & 0xC000) >> 14) == 0x02) argument
181 #define ADXL362_FIFO_HDR_CHECK_TEMP(x) ((((x) & 0xC000) >> 14) == 0x03) argument
195 int16_t acc_xyz[3];
259 uint8_t selected_range: 3;
260 uint8_t accel_odr: 3;