Lines Matching +full:2 +full:x

65 #define ADXL362_STATUS_FIFO_WATERMARK       (1 << 2)
70 #define ADXL362_ACT_INACT_CTL_LINKLOOP(x) (((x) & 0x3) << 4) argument
72 #define ADXL362_ACT_INACT_CTL_INACT_EN (1 << 2)
76 /* ADXL362_ACT_INACT_CTL_LINKLOOP(x) options */
83 #define ADXL362_FIFO_CTL_FIFO_TEMP (1 << 2)
84 #define ADXL362_FIFO_CTL_FIFO_MODE(x) (((x) & 0x3) << 0) argument
86 /* ADXL362_FIFO_CTL_FIFO_MODE(x) options */
89 #define ADXL362_FIFO_STREAM 2
98 #define ADXL362_INTMAP1_FIFO_WATERMARK (1 << 2)
108 #define ADXL362_INTMAP2_FIFO_WATERMARK (1 << 2)
113 #define ADXL362_FILTER_CTL_RANGE(x) (((x) & 0x3) << 6) argument
117 #define ADXL362_FILTER_CTL_ODR(x) (((x) & 0x7) << 0) argument
119 /* ADXL362_FILTER_CTL_RANGE(x) options */
120 #define ADXL362_RANGE_2G 0 /* +/-2 g */
122 #define ADXL362_RANGE_8G 2 /* +/-8 g */
124 /* ADXL362_FILTER_CTL_ODR(x) options */
127 #define ADXL362_ODR_50_HZ 2 /* 50 Hz */
135 #define ADXL362_POWER_CTL_LOW_NOISE(x) (((x) & 0x3) << 4) argument
137 #define ADXL362_POWER_CTL_AUTOSLEEP (1 << 2)
138 #define ADXL362_POWER_CTL_MEASURE(x) (((x) & 0x3) << 0) argument
140 /* ADXL362_POWER_CTL_LOW_NOISE(x) options */
143 #define ADXL362_NOISE_MODE_ULTRALOW 2
145 /* ADXL362_POWER_CTL_MEASURE(x) options */
147 #define ADXL362_MEASURE_ON 2
161 #define ADXL362_STATUS_CHECK_DATA_READY(x) (((x) >> 0) & 0x1) argument
162 #define ADXL362_STATUS_CHECK_INACT(x) (((x) >> 5) & 0x1) argument
163 #define ADXL362_STATUS_CHECK_ACTIVITY(x) (((x) >> 4) & 0x1) argument
164 #define ADXL362_STATUS_CHECK_FIFO_OVR(x) (((x) >> 3) & 0x1) argument
165 #define ADXL362_STATUS_CHECK_FIFO_WTR(x) (((x) >> 2) & 0x1) argument
178 #define ADXL362_FIFO_HDR_CHECK_ACCEL_X(x) ((((x) & 0xC000) >> 14) == 0x00) argument
179 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Y(x) ((((x) & 0xC000) >> 14) == 0x01) argument
180 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Z(x) ((((x) & 0xC000) >> 14) == 0x02) argument
181 #define ADXL362_FIFO_HDR_CHECK_TEMP(x) ((((x) & 0xC000) >> 14) == 0x03) argument
232 uint8_t fifo_ent[2];