Lines Matching full:command

10 /* Bit map for command Register */
106 /* Event/command status */
191 	volatile uint16_t cmd;           /**< Command */
243 	volatile uint32_t cq_ver;            /**< Command Queue Version */
244 	volatile uint32_t cq_cap;            /**< Command Queue Capabilities */
245 	volatile uint32_t cq_cfg;            /**< Command Queue Configuration */
246 	volatile uint32_t cq_ctrl;           /**< Command Queue Control */
247 	volatile uint32_t cq_intr_stat;      /**< Command Queue Interrupt Status */
248 	volatile uint32_t cq_intr_stat_en;   /**< Command Queue Interrupt Status Enable */
249 	volatile uint32_t cq_intr_sig_en;    /**< Command Queue Interrupt Signal Enable */
250 	volatile uint32_t cq_intr_coalesc;   /**< Command Queue Interrupt Coalescing */
251 	volatile uint32_t cq_tdlba;          /**< Command Queue Task Desc List Base Addr */
252 	volatile uint32_t cq_tdlba_upr;      /**< Command Queue Task Desc List Base Addr Upr */
253 	volatile uint32_t cq_task_db;        /**< Command Queue Task DoorBell */
254 	volatile uint32_t cq_task_db_notify; /**< Command Queue Task DoorBell Notify */
255 	volatile uint32_t cq_dev_qstat;      /**< Command Queue Device queue status */
256 	volatile uint32_t cq_dev_pend_task;  /**< Command Queue Device pending tasks */
257 	volatile uint32_t cq_task_clr;       /**< Command Queue Task Clr */
259 	volatile uint32_t cq_ssc1;  /**< Command Queue Send Status Configuration 1 */
260 	volatile uint32_t cq_ssc2;  /**< Command Queue Send Status Configuration 2 */
261 	volatile uint32_t cq_crdct; /**< Command response for direct command */
263 	volatile uint32_t cq_rmem;  /**< Command response mode error mask */
264 	volatile uint32_t cq_terri; /**< Command Queue Task Error Information */
265 	volatile uint32_t cq_cri;   /**< Command Queue Command response index */
266 	volatile uint32_t cq_cra;   /**< Command Queue Command response argument */