Lines Matching defs:emmc_reg
185 struct emmc_reg { struct
186 volatile uint32_t sdma_sysaddr; /**< SDMA System Address */
187 volatile uint16_t block_size; /**< Block Size */
188 volatile uint16_t block_count; /**< Block Count */
189 volatile uint32_t argument; /**< Argument */
190 volatile uint16_t transfer_mode; /**< Transfer Mode */
191 volatile uint16_t cmd; /**< Command */
193 volatile uint32_t resp_01; /**< Response Register 0 & 1 */
194 volatile uint16_t resp_2; /**< Response Register 2*/
195 volatile uint16_t resp_3; /**< Response Register 3 */
196 volatile uint16_t resp_4; /**< Response Register 4 */
197 volatile uint16_t resp_5; /**< Response Register 5 */
198 volatile uint16_t resp_6; /**< Response Register 6 */
199 volatile uint16_t resp_7; /**< Response Register 7 */
200 volatile uint32_t data_port; /**< Buffer Data Port */
201 volatile uint32_t present_state; /**< Present State */
202 volatile uint8_t host_ctrl1; /**< Host Control 1 */
203 volatile uint8_t power_ctrl; /**< Power Control */
204 volatile uint8_t block_gap_ctrl; /**< Block Gap Control */
205 volatile uint8_t wake_up_ctrl; /**< Wakeup Control */
206 volatile uint16_t clock_ctrl; /**< Clock Control */
207 volatile uint8_t timeout_ctrl; /**< Timeout Control */
208 volatile uint8_t sw_reset; /**< Software Reset */
209 volatile uint16_t normal_int_stat; /**< Normal Interrupt Status */
210 volatile uint16_t err_int_stat; /**< Error Interrupt Status */
211 volatile uint16_t normal_int_stat_en; /**< Normal Interrupt Status Enable */
212 volatile uint16_t err_int_stat_en; /**< Error Interrupt Status Enable */
213 volatile uint16_t normal_int_signal_en; /**< Normal Interrupt Signal Enable */
214 volatile uint16_t err_int_signal_en; /**< Error Interrupt Signal Enable */
215 volatile uint16_t auto_cmd_err_stat; /**< Auto CMD Error Status */
216 volatile uint16_t host_ctrl2; /**< Host Control 2 */
217 volatile uint64_t capabilities; /**< Capabilities */
219 volatile uint64_t max_current_cap; /**< Max Current Capabilities */
220 volatile uint16_t force_err_autocmd_stat; /**< Force Event for Auto CMD Error Status*/
221 volatile uint16_t force_err_int_stat; /**< Force Event for Error Interrupt Status */
222 volatile uint8_t adma_err_stat; /**< ADMA Error Status */
223 volatile uint8_t reserved[3];
224 volatile uint32_t adma_sys_addr1; /**< ADMA System Address1 */
225 volatile uint32_t adma_sys_addr2; /**< ADMA System Address2 */
226 volatile uint16_t preset_val_0; /**< Preset Value 0 */
227 volatile uint16_t preset_val_1; /**< Preset Value 1 */
228 volatile uint16_t preset_val_2; /**< Preset Value 2 */
229 volatile uint16_t preset_val_3; /**< Preset Value 3 */
230 volatile uint16_t preset_val_4; /**< Preset Value 4 */
231 volatile uint16_t preset_val_5; /**< Preset Value 5 */
232 volatile uint16_t preset_val_6; /**< Preset Value 6 */
233 volatile uint16_t preset_val_7; /**< Preset Value 7 */
234 volatile uint32_t boot_timeout; /**< Boot Timeout */
235 volatile uint16_t preset_val_8; /**< Preset Value 8 */
236 volatile uint16_t reserved3;
237 volatile uint16_t vendor_reg; /**< Vendor Enhanced strobe */
238 volatile uint16_t reserved4[56];
239 volatile uint32_t reserved5[4];
240 volatile uint16_t slot_intr_stat; /**< Slot Interrupt Status */
241 volatile uint16_t host_cntrl_version; /**< Host Controller Version */
242 volatile uint32_t reserved6[64];
243 volatile uint32_t cq_ver; /**< Command Queue Version */
244 volatile uint32_t cq_cap; /**< Command Queue Capabilities */
245 volatile uint32_t cq_cfg; /**< Command Queue Configuration */
246 volatile uint32_t cq_ctrl; /**< Command Queue Control */
247 volatile uint32_t cq_intr_stat; /**< Command Queue Interrupt Status */
248 volatile uint32_t cq_intr_stat_en; /**< Command Queue Interrupt Status Enable */
249 volatile uint32_t cq_intr_sig_en; /**< Command Queue Interrupt Signal Enable */
250 volatile uint32_t cq_intr_coalesc; /**< Command Queue Interrupt Coalescing */
251 volatile uint32_t cq_tdlba; /**< Command Queue Task Desc List Base Addr */
252 volatile uint32_t cq_tdlba_upr; /**< Command Queue Task Desc List Base Addr Upr */
253 volatile uint32_t cq_task_db; /**< Command Queue Task DoorBell */
254 volatile uint32_t cq_task_db_notify; /**< Command Queue Task DoorBell Notify */
255 volatile uint32_t cq_dev_qstat; /**< Command Queue Device queue status */
256 volatile uint32_t cq_dev_pend_task; /**< Command Queue Device pending tasks */
257 volatile uint32_t cq_task_clr; /**< Command Queue Task Clr */
258 volatile uint32_t reserved7;
259 volatile uint32_t cq_ssc1; /**< Command Queue Send Status Configuration 1 */
260 volatile uint32_t cq_ssc2; /**< Command Queue Send Status Configuration 2 */
261 volatile uint32_t cq_crdct; /**< Command response for direct command */
262 volatile uint32_t reserved8;
263 volatile uint32_t cq_rmem; /**< Command response mode error mask */
264 volatile uint32_t cq_terri; /**< Command Queue Task Error Information */
265 volatile uint32_t cq_cri; /**< Command Queue Command response index */
266 volatile uint32_t cq_cra; /**< Command Queue Command response argument */
267 volatile uint32_t reserved9[425];