Lines Matching refs:regs
60 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in enable_interrupts() local
62 regs->normal_int_stat_en = EMMC_HOST_NORMAL_INTR_MASK; in enable_interrupts()
63 regs->err_int_stat_en = EMMC_HOST_ERROR_INTR_MASK; in enable_interrupts()
64 regs->normal_int_signal_en = EMMC_HOST_NORMAL_INTR_MASK; in enable_interrupts()
65 regs->err_int_signal_en = EMMC_HOST_ERROR_INTR_MASK; in enable_interrupts()
66 regs->timeout_ctrl = EMMC_HOST_MAX_TIMEOUT; in enable_interrupts()
71 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in disable_interrupts() local
74 regs->normal_int_stat_en = EMMC_HOST_NORMAL_INTR_MASK; in disable_interrupts()
75 regs->err_int_stat_en = EMMC_HOST_ERROR_INTR_MASK; in disable_interrupts()
78 regs->normal_int_signal_en &= 0; in disable_interrupts()
79 regs->err_int_signal_en &= 0; in disable_interrupts()
80 regs->timeout_ctrl = EMMC_HOST_MAX_TIMEOUT; in disable_interrupts()
85 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in clear_interrupts() local
87 regs->normal_int_stat = EMMC_HOST_NORMAL_INTR_MASK_CLR; in clear_interrupts()
88 regs->err_int_stat = EMMC_HOST_ERROR_INTR_MASK; in clear_interrupts()
93 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_set_voltage() local
94 bool power_state = regs->power_ctrl & EMMC_HOST_POWER_CTRL_SD_BUS_POWER ? true : false; in emmc_set_voltage()
99 regs->power_ctrl &= ~EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_voltage()
104 if (regs->capabilities & EMMC_HOST_VOL_3_3_V_SUPPORT) { in emmc_set_voltage()
105 regs->host_ctrl2 &= in emmc_set_voltage()
109 regs->power_ctrl = EMMC_HOST_VOL_3_3_V_SELECT; in emmc_set_voltage()
118 if (regs->capabilities & EMMC_HOST_VOL_3_0_V_SUPPORT) { in emmc_set_voltage()
119 regs->host_ctrl2 &= in emmc_set_voltage()
123 regs->power_ctrl = EMMC_HOST_VOL_3_0_V_SELECT; in emmc_set_voltage()
132 if (regs->capabilities & EMMC_HOST_VOL_1_8_V_SUPPORT) { in emmc_set_voltage()
133 regs->host_ctrl2 |= EMMC_HOST_CTRL2_1P8V_SIG_EN in emmc_set_voltage()
137 regs->power_ctrl = EMMC_HOST_VOL_1_8_V_SELECT; in emmc_set_voltage()
151 regs->power_ctrl |= EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_voltage()
159 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_set_power() local
163 regs->power_ctrl |= EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_power()
166 regs->power_ctrl &= ~EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_power()
176 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_disable_clock() local
178 if (regs->present_state & EMMC_HOST_PSTATE_CMD_INHIBIT) { in emmc_disable_clock()
179 LOG_ERR("present_state:%x", regs->present_state); in emmc_disable_clock()
182 if (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT) { in emmc_disable_clock()
183 LOG_ERR("present_state:%x", regs->present_state); in emmc_disable_clock()
187 regs->clock_ctrl &= ~EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_disable_clock()
188 regs->clock_ctrl &= ~EMMC_HOST_SD_CLOCK_EN; in emmc_disable_clock()
190 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) != 0) { in emmc_disable_clock()
199 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_enable_clock() local
201 regs->clock_ctrl |= EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_enable_clock()
203 while ((regs->clock_ctrl & EMMC_HOST_INTERNAL_CLOCK_STABLE) == 0) { in emmc_enable_clock()
208 regs->clock_ctrl |= EMMC_HOST_SD_CLOCK_EN; in emmc_enable_clock()
209 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) == 0) { in emmc_enable_clock()
218 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_clock_set() local
257 base_freq = regs->capabilities >> 8; in emmc_clock_set()
262 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC, in emmc_clock_set()
264 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC, in emmc_clock_set()
274 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in set_timing() local
318 regs->host_ctrl2 |= EMMC_HOST_CTRL2_1P8V_SIG_EN << EMMC_HOST_CTRL2_1P8V_SIG_LOC; in set_timing()
319 SET_BITS(regs->host_ctrl2, EMMC_HOST_CTRL2_UHS_MODE_SEL_LOC, in set_timing()
359 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in poll_cmd_complete() local
364 if (regs->normal_int_stat & EMMC_HOST_CMD_COMPLETE) { in poll_cmd_complete()
365 regs->normal_int_stat = EMMC_HOST_CMD_COMPLETE; in poll_cmd_complete()
374 if (regs->err_int_stat) { in poll_cmd_complete()
375 LOG_ERR("err_int_stat:%x", regs->err_int_stat); in poll_cmd_complete()
376 regs->err_int_stat &= regs->err_int_stat; in poll_cmd_complete()
381 if (regs->adma_err_stat) { in poll_cmd_complete()
382 LOG_ERR("adma error: %x", regs->adma_err_stat); in poll_cmd_complete()
391 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_host_sw_reset() local
394 regs->sw_reset = EMMC_HOST_SW_RESET_REG_DATA; in emmc_host_sw_reset()
396 regs->sw_reset = EMMC_HOST_SW_RESET_REG_CMD; in emmc_host_sw_reset()
398 regs->sw_reset = EMMC_HOST_SW_RESET_REG_ALL; in emmc_host_sw_reset()
401 while (regs->sw_reset != 0) { in emmc_host_sw_reset()
411 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_dma_init() local
442 regs->adma_sys_addr1 = (uint32_t)((uintptr_t)emmc->desc_table & ADDRESS_32BIT_MASK); in emmc_dma_init()
443 regs->adma_sys_addr2 = in emmc_dma_init()
446 LOG_DBG("adma: %llx %x %p", emmc->desc_table[0], regs->adma_sys_addr1, in emmc_dma_init()
450 regs->sdma_sysaddr = (uint32_t)((uintptr_t)data->data); in emmc_dma_init()
451 LOG_DBG("sdma_sysaddr: %x", regs->sdma_sysaddr); in emmc_dma_init()
459 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_init_xfr() local
467 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
470 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
475 SET_BITS(regs->block_size, EMMC_HOST_DMA_BUF_SIZE_LOC, EMMC_HOST_DMA_BUF_SIZE_MASK, in emmc_init_xfr()
477 SET_BITS(regs->block_size, EMMC_HOST_BLOCK_SIZE_LOC, EMMC_HOST_BLOCK_SIZE_MASK, in emmc_init_xfr()
486 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
489 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
493 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
499 regs->block_count = 0; in emmc_init_xfr()
500 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_BLOCK_CNT_EN_LOC, in emmc_init_xfr()
503 regs->block_count = (uint16_t)data->blocks; in emmc_init_xfr()
505 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_BLOCK_CNT_EN_LOC, in emmc_init_xfr()
509 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_MULTI_BLOCK_SEL_LOC, in emmc_init_xfr()
513 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_DATA_DIR_LOC, EMMC_HOST_XFER_DATA_DIR_MASK, in emmc_init_xfr()
518 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_DMA_EN_LOC, EMMC_HOST_XFER_DMA_EN_MASK, in emmc_init_xfr()
521 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_DMA_EN_LOC, EMMC_HOST_XFER_DMA_EN_MASK, in emmc_init_xfr()
527 SET_BITS(regs->block_gap_ctrl, EMMC_HOST_BLOCK_GAP_LOC, EMMC_HOST_BLOCK_GAP_MASK, in emmc_init_xfr()
530 SET_BITS(regs->block_gap_ctrl, EMMC_HOST_BLOCK_GAP_LOC, EMMC_HOST_BLOCK_GAP_MASK, in emmc_init_xfr()
535 regs->timeout_ctrl = data->timeout_ms; in emmc_init_xfr()
575 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in wait_xfr_poll_complete() local
582 if (regs->normal_int_stat & EMMC_HOST_XFER_COMPLETE) { in wait_xfr_poll_complete()
583 regs->normal_int_stat |= EMMC_HOST_XFER_COMPLETE; in wait_xfr_poll_complete()
640 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in update_cmd_response() local
647 resp0 = regs->resp_01; in update_cmd_response()
650 resp1 = regs->resp_2 | (regs->resp_3 << 16u); in update_cmd_response()
651 resp2 = regs->resp_4 | (regs->resp_5 << 16u); in update_cmd_response()
652 resp3 = regs->resp_6 | (regs->resp_7 << 16u); in update_cmd_response()
668 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_host_send_cmd() local
678 if (regs->present_state & EMMC_HOST_PSTATE_CMD_INHIBIT) { in emmc_host_send_cmd()
683 if (config->data_present && (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT)) { in emmc_host_send_cmd()
695 regs->argument = sdhc_cmd->arg; in emmc_host_send_cmd()
703 regs->cmd = cmd_reg; in emmc_host_send_cmd()
705 LOG_DBG("CMD REG:%x %x", cmd_reg, regs->cmd); in emmc_host_send_cmd()
743 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_reset() local
747 if (!(regs->present_state & EMMC_HOST_PSTATE_CARD_INSERTED)) { in emmc_reset()
769 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in read_data_port() local
796 while ((regs->present_state & EMMC_HOST_PSTATE_BUF_READ_EN) == 0) { in read_data_port()
801 if (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT) { in read_data_port()
803 *data = regs->data_port; in read_data_port()
815 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in write_data_port() local
829 while ((regs->present_state & EMMC_HOST_PSTATE_BUF_WRITE_EN) == 0) { in write_data_port()
840 if (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT) { in write_data_port()
842 regs->data_port = *data; in write_data_port()
862 while ((regs->present_state & EMMC_HOST_PSTATE_BUF_WRITE_EN) == 0) { in write_data_port()
1010 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_set_io() local
1044 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_EXT_DAT_WIDTH_LOC, in emmc_set_io()
1048 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DAT_WIDTH_LOC, in emmc_set_io()
1096 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_get_card_present() local
1100 emmc->card_present = (bool)((regs->present_state >> 16u) & 1u); in emmc_get_card_present()
1112 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_execute_tuning() local
1116 regs->host_ctrl2 |= EMMC_HOST_START_TUNING; in emmc_execute_tuning()
1117 while (!(regs->host_ctrl2 & EMMC_HOST_START_TUNING)) { in emmc_execute_tuning()
1121 if (regs->host_ctrl2 & EMMC_HOST_TUNING_SUCCESS) { in emmc_execute_tuning()
1133 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_card_busy() local
1137 if (regs->present_state & 7u) { in emmc_card_busy()
1148 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_get_host_props() local
1149 uint64_t cap = regs->capabilities; in emmc_get_host_props()
1183 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_isr() local
1185 if (regs->normal_int_stat & EMMC_HOST_CMD_COMPLETE) { in emmc_isr()
1186 regs->normal_int_stat |= EMMC_HOST_CMD_COMPLETE; in emmc_isr()
1190 if (regs->normal_int_stat & EMMC_HOST_XFER_COMPLETE) { in emmc_isr()
1191 regs->normal_int_stat |= EMMC_HOST_XFER_COMPLETE; in emmc_isr()
1195 if (regs->normal_int_stat & EMMC_HOST_DMA_INTR) { in emmc_isr()
1196 regs->normal_int_stat |= EMMC_HOST_DMA_INTR; in emmc_isr()
1200 if (regs->normal_int_stat & EMMC_HOST_BUF_WR_READY) { in emmc_isr()
1201 regs->normal_int_stat |= EMMC_HOST_BUF_WR_READY; in emmc_isr()
1205 if (regs->normal_int_stat & EMMC_HOST_BUF_RD_READY) { in emmc_isr()
1206 regs->normal_int_stat |= EMMC_HOST_BUF_RD_READY; in emmc_isr()
1210 if (regs->err_int_stat) { in emmc_isr()
1211 LOG_ERR("err int:%x", regs->err_int_stat); in emmc_isr()
1212 k_event_post(&emmc->irq_event, ERR_INTR_STATUS_EVENT(regs->err_int_stat)); in emmc_isr()
1213 if (regs->err_int_stat & EMMC_HOST_DMA_TXFR_ERR) { in emmc_isr()
1214 regs->err_int_stat |= EMMC_HOST_DMA_TXFR_ERR; in emmc_isr()
1216 regs->err_int_stat |= regs->err_int_stat; in emmc_isr()
1220 if (regs->normal_int_stat) { in emmc_isr()
1221 k_event_post(&emmc->irq_event, regs->normal_int_stat); in emmc_isr()
1222 regs->normal_int_stat |= regs->normal_int_stat; in emmc_isr()
1225 if (regs->adma_err_stat) { in emmc_isr()
1226 LOG_ERR("adma err:%x", regs->adma_err_stat); in emmc_isr()