Lines Matching +full:min +full:- +full:bus +full:- +full:freq
4 * SPDX-License-Identifier: Apache-2.0
62 regs->normal_int_stat_en = EMMC_HOST_NORMAL_INTR_MASK; in enable_interrupts()
63 regs->err_int_stat_en = EMMC_HOST_ERROR_INTR_MASK; in enable_interrupts()
64 regs->normal_int_signal_en = EMMC_HOST_NORMAL_INTR_MASK; in enable_interrupts()
65 regs->err_int_signal_en = EMMC_HOST_ERROR_INTR_MASK; in enable_interrupts()
66 regs->timeout_ctrl = EMMC_HOST_MAX_TIMEOUT; in enable_interrupts()
74 regs->normal_int_stat_en = EMMC_HOST_NORMAL_INTR_MASK; in disable_interrupts()
75 regs->err_int_stat_en = EMMC_HOST_ERROR_INTR_MASK; in disable_interrupts()
78 regs->normal_int_signal_en &= 0; in disable_interrupts()
79 regs->err_int_signal_en &= 0; in disable_interrupts()
80 regs->timeout_ctrl = EMMC_HOST_MAX_TIMEOUT; in disable_interrupts()
87 regs->normal_int_stat = EMMC_HOST_NORMAL_INTR_MASK_CLR; in clear_interrupts()
88 regs->err_int_stat = EMMC_HOST_ERROR_INTR_MASK; in clear_interrupts()
94 bool power_state = regs->power_ctrl & EMMC_HOST_POWER_CTRL_SD_BUS_POWER ? true : false; in emmc_set_voltage()
98 /* Turn OFF Bus Power before config clock */ in emmc_set_voltage()
99 regs->power_ctrl &= ~EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_voltage()
104 if (regs->capabilities & EMMC_HOST_VOL_3_3_V_SUPPORT) { in emmc_set_voltage()
105 regs->host_ctrl2 &= in emmc_set_voltage()
109 regs->power_ctrl = EMMC_HOST_VOL_3_3_V_SELECT; in emmc_set_voltage()
113 ret = -ENOTSUP; in emmc_set_voltage()
118 if (regs->capabilities & EMMC_HOST_VOL_3_0_V_SUPPORT) { in emmc_set_voltage()
119 regs->host_ctrl2 &= in emmc_set_voltage()
123 regs->power_ctrl = EMMC_HOST_VOL_3_0_V_SELECT; in emmc_set_voltage()
127 ret = -ENOTSUP; in emmc_set_voltage()
132 if (regs->capabilities & EMMC_HOST_VOL_1_8_V_SUPPORT) { in emmc_set_voltage()
133 regs->host_ctrl2 |= EMMC_HOST_CTRL2_1P8V_SIG_EN in emmc_set_voltage()
137 regs->power_ctrl = EMMC_HOST_VOL_1_8_V_SELECT; in emmc_set_voltage()
141 ret = -ENOTSUP; in emmc_set_voltage()
146 ret = -EINVAL; in emmc_set_voltage()
150 /* Turn ON Bus Power */ in emmc_set_voltage()
151 regs->power_ctrl |= EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_voltage()
162 /* Turn ON Bus Power */ in emmc_set_power()
163 regs->power_ctrl |= EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_power()
165 /* Turn OFF Bus Power */ in emmc_set_power()
166 regs->power_ctrl &= ~EMMC_HOST_POWER_CTRL_SD_BUS_POWER; in emmc_set_power()
178 if (regs->present_state & EMMC_HOST_PSTATE_CMD_INHIBIT) { in emmc_disable_clock()
179 LOG_ERR("present_state:%x", regs->present_state); in emmc_disable_clock()
182 if (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT) { in emmc_disable_clock()
183 LOG_ERR("present_state:%x", regs->present_state); in emmc_disable_clock()
187 regs->clock_ctrl &= ~EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_disable_clock()
188 regs->clock_ctrl &= ~EMMC_HOST_SD_CLOCK_EN; in emmc_disable_clock()
190 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) != 0) { in emmc_disable_clock()
201 regs->clock_ctrl |= EMMC_HOST_INTERNAL_CLOCK_EN; in emmc_enable_clock()
203 while ((regs->clock_ctrl & EMMC_HOST_INTERNAL_CLOCK_STABLE) == 0) { in emmc_enable_clock()
208 regs->clock_ctrl |= EMMC_HOST_SD_CLOCK_EN; in emmc_enable_clock()
209 while ((regs->clock_ctrl & EMMC_HOST_SD_CLOCK_EN) == 0) { in emmc_enable_clock()
221 float freq; in emmc_clock_set() local
226 freq = EMMC_HOST_CLK_FREQ_400K; in emmc_clock_set()
231 freq = EMMC_HOST_CLK_FREQ_25M; in emmc_clock_set()
236 freq = EMMC_HOST_CLK_FREQ_50M; in emmc_clock_set()
240 freq = EMMC_HOST_CLK_FREQ_100M; in emmc_clock_set()
244 freq = EMMC_HOST_CLK_FREQ_200M; in emmc_clock_set()
257 base_freq = regs->capabilities >> 8; in emmc_clock_set()
258 clock_divider = (int)(base_freq / (freq * 2)); in emmc_clock_set()
262 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC, in emmc_clock_set()
264 SET_BITS(regs->clock_ctrl, EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC, in emmc_clock_set()
310 ret = -ENOTSUP; in set_timing()
316 return -EIO; in set_timing()
318 regs->host_ctrl2 |= EMMC_HOST_CTRL2_1P8V_SIG_EN << EMMC_HOST_CTRL2_1P8V_SIG_LOC; in set_timing()
319 SET_BITS(regs->host_ctrl2, EMMC_HOST_CTRL2_UHS_MODE_SEL_LOC, in set_timing()
340 events = k_event_wait(&emmc->irq_event, in wait_for_cmd_complete()
348 ret = -EIO; in wait_for_cmd_complete()
351 ret = -EAGAIN; in wait_for_cmd_complete()
360 int ret = -EAGAIN; in poll_cmd_complete()
364 if (regs->normal_int_stat & EMMC_HOST_CMD_COMPLETE) { in poll_cmd_complete()
365 regs->normal_int_stat = EMMC_HOST_CMD_COMPLETE; in poll_cmd_complete()
371 retry--; in poll_cmd_complete()
374 if (regs->err_int_stat) { in poll_cmd_complete()
375 LOG_ERR("err_int_stat:%x", regs->err_int_stat); in poll_cmd_complete()
376 regs->err_int_stat &= regs->err_int_stat; in poll_cmd_complete()
377 ret = -EIO; in poll_cmd_complete()
381 if (regs->adma_err_stat) { in poll_cmd_complete()
382 LOG_ERR("adma error: %x", regs->adma_err_stat); in poll_cmd_complete()
383 ret = -EIO; in poll_cmd_complete()
394 regs->sw_reset = EMMC_HOST_SW_RESET_REG_DATA; in emmc_host_sw_reset()
396 regs->sw_reset = EMMC_HOST_SW_RESET_REG_CMD; in emmc_host_sw_reset()
398 regs->sw_reset = EMMC_HOST_SW_RESET_REG_ALL; in emmc_host_sw_reset()
401 while (regs->sw_reset != 0) { in emmc_host_sw_reset()
410 struct emmc_data *emmc = dev->data; in emmc_dma_init()
414 sys_cache_data_flush_range(data->data, (data->blocks * data->block_size)); in emmc_dma_init()
418 uint8_t *buff = data->data; in emmc_dma_init()
421 memset(emmc->desc_table, 0, sizeof(emmc->desc_table)); in emmc_dma_init()
424 __ASSERT_NO_MSG(data->blocks < CONFIG_INTEL_EMMC_HOST_ADMA_DESC_SIZE); in emmc_dma_init()
426 for (int i = 0; i < data->blocks; i++) { in emmc_dma_init()
427 emmc->desc_table[i] = ((uint64_t)buff) << EMMC_HOST_ADMA_BUFF_ADD_LOC; in emmc_dma_init()
428 emmc->desc_table[i] |= data->block_size << EMMC_HOST_ADMA_BUFF_LEN_LOC; in emmc_dma_init()
430 if (i == (data->blocks - 1u)) { in emmc_dma_init()
431 emmc->desc_table[i] |= EMMC_HOST_ADMA_BUFF_LINK_LAST; in emmc_dma_init()
432 emmc->desc_table[i] |= EMMC_HOST_ADMA_INTR_EN; in emmc_dma_init()
433 emmc->desc_table[i] |= EMMC_HOST_ADMA_BUFF_LAST; in emmc_dma_init()
435 emmc->desc_table[i] |= EMMC_HOST_ADMA_BUFF_LINK_NEXT; in emmc_dma_init()
437 emmc->desc_table[i] |= EMMC_HOST_ADMA_BUFF_VALID; in emmc_dma_init()
438 buff += data->block_size; in emmc_dma_init()
439 LOG_DBG("desc_table:%llx", emmc->desc_table[i]); in emmc_dma_init()
442 regs->adma_sys_addr1 = (uint32_t)((uintptr_t)emmc->desc_table & ADDRESS_32BIT_MASK); in emmc_dma_init()
443 regs->adma_sys_addr2 = in emmc_dma_init()
444 (uint32_t)(((uintptr_t)emmc->desc_table >> 32) & ADDRESS_32BIT_MASK); in emmc_dma_init()
446 LOG_DBG("adma: %llx %x %p", emmc->desc_table[0], regs->adma_sys_addr1, in emmc_dma_init()
447 emmc->desc_table); in emmc_dma_init()
450 regs->sdma_sysaddr = (uint32_t)((uintptr_t)data->data); in emmc_dma_init()
451 LOG_DBG("sdma_sysaddr: %x", regs->sdma_sysaddr); in emmc_dma_init()
458 struct emmc_data *emmc = dev->data; in emmc_init_xfr()
467 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
470 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DMA_SEL_LOC, in emmc_init_xfr()
475 SET_BITS(regs->block_size, EMMC_HOST_DMA_BUF_SIZE_LOC, EMMC_HOST_DMA_BUF_SIZE_MASK, in emmc_init_xfr()
477 SET_BITS(regs->block_size, EMMC_HOST_BLOCK_SIZE_LOC, EMMC_HOST_BLOCK_SIZE_MASK, in emmc_init_xfr()
478 data->block_size); in emmc_init_xfr()
479 if (data->blocks > 1) { in emmc_init_xfr()
484 emmc->host_io.timing == SDHC_TIMING_SDR104) { in emmc_init_xfr()
486 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
489 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
493 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_AUTO_CMD_EN_LOC, in emmc_init_xfr()
499 regs->block_count = 0; in emmc_init_xfr()
500 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_BLOCK_CNT_EN_LOC, in emmc_init_xfr()
503 regs->block_count = (uint16_t)data->blocks; in emmc_init_xfr()
505 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_BLOCK_CNT_EN_LOC, in emmc_init_xfr()
509 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_MULTI_BLOCK_SEL_LOC, in emmc_init_xfr()
513 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_DATA_DIR_LOC, EMMC_HOST_XFER_DATA_DIR_MASK, in emmc_init_xfr()
518 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_DMA_EN_LOC, EMMC_HOST_XFER_DMA_EN_MASK, in emmc_init_xfr()
521 SET_BITS(regs->transfer_mode, EMMC_HOST_XFER_DMA_EN_LOC, EMMC_HOST_XFER_DMA_EN_MASK, in emmc_init_xfr()
527 SET_BITS(regs->block_gap_ctrl, EMMC_HOST_BLOCK_GAP_LOC, EMMC_HOST_BLOCK_GAP_MASK, in emmc_init_xfr()
530 SET_BITS(regs->block_gap_ctrl, EMMC_HOST_BLOCK_GAP_LOC, EMMC_HOST_BLOCK_GAP_MASK, in emmc_init_xfr()
535 regs->timeout_ctrl = data->timeout_ms; in emmc_init_xfr()
542 struct emmc_data *emmc = dev->data; in wait_xfr_intr_complete()
555 events = k_event_wait(&emmc->irq_event, in wait_xfr_intr_complete()
564 ret = -EIO; in wait_xfr_intr_complete()
567 ret = -EAGAIN; in wait_xfr_intr_complete()
576 int ret = -EAGAIN; in wait_xfr_poll_complete()
582 if (regs->normal_int_stat & EMMC_HOST_XFER_COMPLETE) { in wait_xfr_poll_complete()
583 regs->normal_int_stat |= EMMC_HOST_XFER_COMPLETE; in wait_xfr_poll_complete()
589 retry--; in wait_xfr_poll_complete()
643 if (sdhc_cmd->response_type == SD_RSP_TYPE_NONE) { in update_cmd_response()
647 resp0 = regs->resp_01; in update_cmd_response()
649 if (sdhc_cmd->response_type == SD_RSP_TYPE_R2) { in update_cmd_response()
650 resp1 = regs->resp_2 | (regs->resp_3 << 16u); in update_cmd_response()
651 resp2 = regs->resp_4 | (regs->resp_5 << 16u); in update_cmd_response()
652 resp3 = regs->resp_6 | (regs->resp_7 << 16u); in update_cmd_response()
656 sdhc_cmd->response[0u] = resp3; in update_cmd_response()
657 sdhc_cmd->response[1U] = resp2; in update_cmd_response()
658 sdhc_cmd->response[2U] = resp1; in update_cmd_response()
659 sdhc_cmd->response[3U] = resp0; in update_cmd_response()
662 sdhc_cmd->response[0u] = resp0; in update_cmd_response()
669 struct emmc_data *emmc = dev->data; in emmc_host_send_cmd()
670 struct sdhc_command *sdhc_cmd = config->sdhc_cmd; in emmc_host_send_cmd()
671 enum emmc_response_type resp_type = emmc_decode_resp_type(sdhc_cmd->response_type); in emmc_host_send_cmd()
678 if (regs->present_state & EMMC_HOST_PSTATE_CMD_INHIBIT) { in emmc_host_send_cmd()
680 return -EBUSY; in emmc_host_send_cmd()
683 if (config->data_present && (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT)) { in emmc_host_send_cmd()
685 return -EBUSY; in emmc_host_send_cmd()
690 return -EINVAL; in emmc_host_send_cmd()
693 k_event_clear(&emmc->irq_event, EMMC_HOST_CMD_COMPLETE); in emmc_host_send_cmd()
695 regs->argument = sdhc_cmd->arg; in emmc_host_send_cmd()
697 cmd_reg = config->cmd_idx << EMMC_HOST_CMD_INDEX_LOC | in emmc_host_send_cmd()
698 config->cmd_type << EMMC_HOST_CMD_TYPE_LOC | in emmc_host_send_cmd()
699 config->data_present << EMMC_HOST_CMD_DATA_PRESENT_LOC | in emmc_host_send_cmd()
700 config->idx_check_en << EMMC_HOST_CMD_IDX_CHECK_EN_LOC | in emmc_host_send_cmd()
701 config->crc_check_en << EMMC_HOST_CMD_CRC_CHECK_EN_LOC | in emmc_host_send_cmd()
703 regs->cmd = cmd_reg; in emmc_host_send_cmd()
705 LOG_DBG("CMD REG:%x %x", cmd_reg, regs->cmd); in emmc_host_send_cmd()
707 ret = wait_for_cmd_complete(emmc, sdhc_cmd->timeout_ms); in emmc_host_send_cmd()
709 ret = poll_cmd_complete(dev, sdhc_cmd->timeout_ms); in emmc_host_send_cmd()
712 LOG_ERR("Error on send cmd: %d, status:%d", config->cmd_idx, ret); in emmc_host_send_cmd()
723 struct emmc_data *emmc = dev->data; in emmc_stop_transfer()
727 hdc_cmd.arg = emmc->rca << EMMC_HOST_RCA_SHIFT; in emmc_stop_transfer()
747 if (!(regs->present_state & EMMC_HOST_PSTATE_CARD_INSERTED)) { in emmc_reset()
749 return -ENODEV; in emmc_reset()
768 struct emmc_data *emmc = dev->data; in read_data_port()
770 uint32_t block_size = sdhc->block_size; in read_data_port()
771 uint32_t i, block_cnt = sdhc->blocks; in read_data_port()
772 uint32_t *data = (uint32_t *)sdhc->data; in read_data_port()
775 if (sdhc->timeout_ms == SDHC_TIMEOUT_FOREVER) { in read_data_port()
778 wait_time = K_MSEC(sdhc->timeout_ms); in read_data_port()
783 while (block_cnt--) { in read_data_port()
787 events = k_event_wait(&emmc->irq_event, EMMC_HOST_BUF_RD_READY, false, in read_data_port()
789 k_event_clear(&emmc->irq_event, EMMC_HOST_BUF_RD_READY); in read_data_port()
792 (sdhc->blocks - block_cnt)); in read_data_port()
793 return -EIO; in read_data_port()
796 while ((regs->present_state & EMMC_HOST_PSTATE_BUF_READ_EN) == 0) { in read_data_port()
801 if (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT) { in read_data_port()
802 for (i = block_size >> 2u; i != 0u; i--) { in read_data_port()
803 *data = regs->data_port; in read_data_port()
809 return wait_xfr_complete(dev, sdhc->timeout_ms); in read_data_port()
814 struct emmc_data *emmc = dev->data; in write_data_port()
816 uint32_t block_size = sdhc->block_size; in write_data_port()
817 uint32_t i, block_cnt = sdhc->blocks; in write_data_port()
818 uint32_t *data = (uint32_t *)sdhc->data; in write_data_port()
821 if (sdhc->timeout_ms == SDHC_TIMEOUT_FOREVER) { in write_data_port()
824 wait_time = K_MSEC(sdhc->timeout_ms); in write_data_port()
829 while ((regs->present_state & EMMC_HOST_PSTATE_BUF_WRITE_EN) == 0) { in write_data_port()
837 k_event_clear(&emmc->irq_event, EMMC_HOST_BUF_WR_READY); in write_data_port()
840 if (regs->present_state & EMMC_HOST_PSTATE_DAT_INHIBIT) { in write_data_port()
841 for (i = block_size >> 2u; i != 0u; i--) { in write_data_port()
842 regs->data_port = *data; in write_data_port()
849 if (!(--block_cnt)) { in write_data_port()
853 events = k_event_wait(&emmc->irq_event, EMMC_HOST_BUF_WR_READY, false, in write_data_port()
855 k_event_clear(&emmc->irq_event, EMMC_HOST_BUF_WR_READY); in write_data_port()
859 return -EIO; in write_data_port()
862 while ((regs->present_state & EMMC_HOST_PSTATE_BUF_WRITE_EN) == 0) { in write_data_port()
868 return wait_xfr_complete(dev, sdhc->timeout_ms); in write_data_port()
911 ret = wait_xfr_complete(dev, data->timeout_ms); in emmc_send_cmd_data()
926 struct emmc_data *emmc = dev->data; in emmc_xfr()
941 k_event_clear(&emmc->irq_event, EMMC_HOST_XFER_COMPLETE); in emmc_xfr()
942 k_event_clear(&emmc->irq_event, read ? EMMC_HOST_BUF_RD_READY : EMMC_HOST_BUF_WR_READY); in emmc_xfr()
944 if (data->blocks > 1) { in emmc_xfr()
957 ret = wait_xfr_complete(dev, data->timeout_ms); in emmc_xfr()
979 switch (cmd->opcode) { in emmc_request()
998 ret = emmc_send_cmd_data(dev, cmd->opcode, cmd, data, true); in emmc_request()
1001 ret = emmc_send_cmd_no_data(dev, cmd->opcode, cmd); in emmc_request()
1009 struct emmc_data *emmc = dev->data; in emmc_set_io()
1011 struct sdhc_io *host_io = &emmc->host_io; in emmc_set_io()
1014 LOG_DBG("emmc I/O: DW %d, Clk %d Hz, card power state %s, voltage %s", ios->bus_width, in emmc_set_io()
1015 ios->clock, ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF", in emmc_set_io()
1016 ios->signal_voltage == SD_VOL_1_8_V ? "1.8V" : "3.3V"); in emmc_set_io()
1018 if (ios->clock && (ios->clock > emmc->props.f_max || ios->clock < emmc->props.f_min)) { in emmc_set_io()
1019 LOG_ERR("Invalid argument for clock freq: %d Support max:%d and Min:%d", ios->clock, in emmc_set_io()
1020 emmc->props.f_max, emmc->props.f_min); in emmc_set_io()
1021 return -EINVAL; in emmc_set_io()
1025 if (host_io->clock != ios->clock) { in emmc_set_io()
1026 LOG_DBG("Clock: %d", host_io->clock); in emmc_set_io()
1027 if (ios->clock != 0) { in emmc_set_io()
1029 LOG_DBG("CLOCK: %d", ios->clock); in emmc_set_io()
1030 if (!emmc_clock_set(dev, ios->clock)) { in emmc_set_io()
1031 return -ENOTSUP; in emmc_set_io()
1036 host_io->clock = ios->clock; in emmc_set_io()
1040 if (host_io->bus_width != ios->bus_width) { in emmc_set_io()
1041 LOG_DBG("bus_width: %d", host_io->bus_width); in emmc_set_io()
1043 if (ios->bus_width == SDHC_BUS_WIDTH4BIT) { in emmc_set_io()
1044 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_EXT_DAT_WIDTH_LOC, in emmc_set_io()
1046 ios->bus_width == SDHC_BUS_WIDTH8BIT ? 1 : 0); in emmc_set_io()
1048 SET_BITS(regs->host_ctrl1, EMMC_HOST_CTRL1_DAT_WIDTH_LOC, in emmc_set_io()
1050 ios->bus_width == SDHC_BUS_WIDTH4BIT ? 1 : 0); in emmc_set_io()
1052 host_io->bus_width = ios->bus_width; in emmc_set_io()
1056 if (ios->signal_voltage != host_io->signal_voltage) { in emmc_set_io()
1057 LOG_DBG("signal_voltage: %d", ios->signal_voltage); in emmc_set_io()
1058 ret = emmc_set_voltage(dev, ios->signal_voltage); in emmc_set_io()
1063 host_io->signal_voltage = ios->signal_voltage; in emmc_set_io()
1067 if (host_io->power_mode != ios->power_mode) { in emmc_set_io()
1068 LOG_DBG("power_mode: %d", ios->power_mode); in emmc_set_io()
1070 ret = emmc_set_power(dev, ios->power_mode); in emmc_set_io()
1072 LOG_ERR("Set Bus power failed:%d", ret); in emmc_set_io()
1075 host_io->power_mode = ios->power_mode; in emmc_set_io()
1079 if (host_io->timing != ios->timing) { in emmc_set_io()
1080 LOG_DBG("timing: %d", ios->timing); in emmc_set_io()
1082 ret = set_timing(dev, ios->timing); in emmc_set_io()
1087 host_io->timing = ios->timing; in emmc_set_io()
1095 struct emmc_data *emmc = dev->data; in emmc_get_card_present()
1100 emmc->card_present = (bool)((regs->present_state >> 16u) & 1u); in emmc_get_card_present()
1102 if (!emmc->card_present) { in emmc_get_card_present()
1106 return ((int)emmc->card_present); in emmc_get_card_present()
1116 regs->host_ctrl2 |= EMMC_HOST_START_TUNING; in emmc_execute_tuning()
1117 while (!(regs->host_ctrl2 & EMMC_HOST_START_TUNING)) { in emmc_execute_tuning()
1121 if (regs->host_ctrl2 & EMMC_HOST_TUNING_SUCCESS) { in emmc_execute_tuning()
1125 return -EIO; in emmc_execute_tuning()
1137 if (regs->present_state & 7u) { in emmc_card_busy()
1146 struct emmc_data *emmc = dev->data; in emmc_get_host_props()
1147 const struct emmc_config *config = dev->config; in emmc_get_host_props()
1149 uint64_t cap = regs->capabilities; in emmc_get_host_props()
1154 props->f_max = config->max_bus_freq; in emmc_get_host_props()
1155 props->f_min = config->min_bus_freq; in emmc_get_host_props()
1156 props->power_delay = config->power_delay_ms; in emmc_get_host_props()
1158 props->host_caps.vol_180_support = (bool)(cap & BIT(26u)); in emmc_get_host_props()
1159 props->host_caps.vol_300_support = (bool)(cap & BIT(25u)); in emmc_get_host_props()
1160 props->host_caps.vol_330_support = (bool)(bool)(cap & BIT(24u)); in emmc_get_host_props()
1161 props->host_caps.suspend_res_support = false; in emmc_get_host_props()
1162 props->host_caps.sdma_support = (bool)(cap & BIT(22u)); in emmc_get_host_props()
1163 props->host_caps.high_spd_support = (bool)(cap & BIT(21u)); in emmc_get_host_props()
1164 props->host_caps.adma_2_support = (bool)(cap & BIT(19u)); in emmc_get_host_props()
1166 props->host_caps.max_blk_len = (cap >> 16u) & 0x3u; in emmc_get_host_props()
1167 props->host_caps.ddr50_support = (bool)(cap & BIT(34u)); in emmc_get_host_props()
1168 props->host_caps.sdr104_support = (bool)(cap & BIT(33u)); in emmc_get_host_props()
1169 props->host_caps.sdr50_support = (bool)(cap & BIT(32u)); in emmc_get_host_props()
1170 props->host_caps.bus_8_bit_support = true; in emmc_get_host_props()
1171 props->host_caps.bus_4_bit_support = true; in emmc_get_host_props()
1172 props->host_caps.hs200_support = (bool)config->hs200_mode; in emmc_get_host_props()
1173 props->host_caps.hs400_support = (bool)config->hs400_mode; in emmc_get_host_props()
1175 emmc->props = *props; in emmc_get_host_props()
1182 struct emmc_data *emmc = dev->data; in emmc_isr()
1185 if (regs->normal_int_stat & EMMC_HOST_CMD_COMPLETE) { in emmc_isr()
1186 regs->normal_int_stat |= EMMC_HOST_CMD_COMPLETE; in emmc_isr()
1187 k_event_post(&emmc->irq_event, EMMC_HOST_CMD_COMPLETE); in emmc_isr()
1190 if (regs->normal_int_stat & EMMC_HOST_XFER_COMPLETE) { in emmc_isr()
1191 regs->normal_int_stat |= EMMC_HOST_XFER_COMPLETE; in emmc_isr()
1192 k_event_post(&emmc->irq_event, EMMC_HOST_XFER_COMPLETE); in emmc_isr()
1195 if (regs->normal_int_stat & EMMC_HOST_DMA_INTR) { in emmc_isr()
1196 regs->normal_int_stat |= EMMC_HOST_DMA_INTR; in emmc_isr()
1197 k_event_post(&emmc->irq_event, EMMC_HOST_DMA_INTR); in emmc_isr()
1200 if (regs->normal_int_stat & EMMC_HOST_BUF_WR_READY) { in emmc_isr()
1201 regs->normal_int_stat |= EMMC_HOST_BUF_WR_READY; in emmc_isr()
1202 k_event_post(&emmc->irq_event, EMMC_HOST_BUF_WR_READY); in emmc_isr()
1205 if (regs->normal_int_stat & EMMC_HOST_BUF_RD_READY) { in emmc_isr()
1206 regs->normal_int_stat |= EMMC_HOST_BUF_RD_READY; in emmc_isr()
1207 k_event_post(&emmc->irq_event, EMMC_HOST_BUF_RD_READY); in emmc_isr()
1210 if (regs->err_int_stat) { in emmc_isr()
1211 LOG_ERR("err int:%x", regs->err_int_stat); in emmc_isr()
1212 k_event_post(&emmc->irq_event, ERR_INTR_STATUS_EVENT(regs->err_int_stat)); in emmc_isr()
1213 if (regs->err_int_stat & EMMC_HOST_DMA_TXFR_ERR) { in emmc_isr()
1214 regs->err_int_stat |= EMMC_HOST_DMA_TXFR_ERR; in emmc_isr()
1216 regs->err_int_stat |= regs->err_int_stat; in emmc_isr()
1220 if (regs->normal_int_stat) { in emmc_isr()
1221 k_event_post(&emmc->irq_event, regs->normal_int_stat); in emmc_isr()
1222 regs->normal_int_stat |= regs->normal_int_stat; in emmc_isr()
1225 if (regs->adma_err_stat) { in emmc_isr()
1226 LOG_ERR("adma err:%x", regs->adma_err_stat); in emmc_isr()
1232 struct emmc_data *emmc = dev->data; in emmc_init()
1233 const struct emmc_config *config = dev->config; in emmc_init()
1235 k_sem_init(&emmc->lock, 1, 1); in emmc_init()
1236 k_event_init(&emmc->irq_event); in emmc_init()
1239 if (config->pcie) { in emmc_init()
1242 if (config->pcie->bdf == PCIE_BDF_NONE) { in emmc_init()
1243 LOG_ERR("Cannot probe eMMC PCI device: %x", config->pcie->id); in emmc_init()
1244 return -ENODEV; in emmc_init()
1247 if (!pcie_probe_mbar(config->pcie->bdf, 0, &mbar)) { in emmc_init()
1249 return -EINVAL; in emmc_init()
1252 pcie_get_mbar(config->pcie->bdf, 0, &mbar); in emmc_init()
1253 pcie_set_cmd(config->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true); in emmc_init()
1255 pcie_set_cmd(config->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true); in emmc_init()
1265 config->config_func(dev); in emmc_init()
1303 const struct emmc_config *const dev_cfg = port->config; \
1304 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1309 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, DT_INST_IRQ(n, priority), \
1312 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \