Lines Matching +full:clear +full:- +full:command +full:- +full:delay +full:- +full:us
4 * SPDX-License-Identifier: Apache-2.0
101 struct usdhc_data *data = dev->data; in transfer_complete_cb()
104 data->transfer_status |= TRANSFER_DATA_FAILED; in transfer_complete_cb()
106 data->transfer_status |= TRANSFER_DATA_COMPLETE; in transfer_complete_cb()
108 data->transfer_status |= TRANSFER_CMD_FAILED; in transfer_complete_cb()
110 data->transfer_status |= TRANSFER_CMD_COMPLETE; in transfer_complete_cb()
112 k_sem_give(&data->transfer_sem); in transfer_complete_cb()
119 struct usdhc_data *data = dev->data; in sdio_interrupt_cb()
121 if (data->sdhc_cb) { in sdio_interrupt_cb()
122 data->sdhc_cb(dev, SDHC_INT_SDIO, data->sdhc_cb_user_data); in sdio_interrupt_cb()
129 struct usdhc_data *data = dev->data; in card_inserted_cb()
131 if (data->sdhc_cb) { in card_inserted_cb()
132 data->sdhc_cb(dev, SDHC_INT_INSERTED, data->sdhc_cb_user_data); in card_inserted_cb()
139 struct usdhc_data *data = dev->data; in card_removed_cb()
141 if (data->sdhc_cb) { in card_removed_cb()
142 data->sdhc_cb(dev, SDHC_INT_REMOVED, data->sdhc_cb_user_data); in card_removed_cb()
151 const struct device *dev = data->dev; in card_detect_gpio_cb()
152 const struct usdhc_config *cfg = dev->config; in card_detect_gpio_cb()
154 if (data->sdhc_cb) { in card_detect_gpio_cb()
155 if (gpio_pin_get_dt(&cfg->detect_gpio)) { in card_detect_gpio_cb()
156 data->sdhc_cb(dev, SDHC_INT_INSERTED, data->sdhc_cb_user_data); in card_detect_gpio_cb()
158 data->sdhc_cb(dev, SDHC_INT_REMOVED, data->sdhc_cb_user_data); in card_detect_gpio_cb()
176 ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_NOPULL); in imx_usdhc_dat3_pull()
183 /* Power off the card to clear DAT3 legacy status */ in imx_usdhc_dat3_pull()
184 if (cfg->pwr_gpio.port) { in imx_usdhc_dat3_pull()
185 ret = gpio_pin_set_dt(&cfg->pwr_gpio, 0); in imx_usdhc_dat3_pull()
189 /* Delay for card power off to complete */ in imx_usdhc_dat3_pull()
191 ret = gpio_pin_set_dt(&cfg->pwr_gpio, 1); in imx_usdhc_dat3_pull()
192 /* Delay for power on */ in imx_usdhc_dat3_pull()
204 * Reset SDHC after command error
208 const struct usdhc_config *cfg = dev->config; in imx_usdhc_error_recovery()
209 uint32_t status = USDHC_GetPresentStatusFlags(cfg->base); in imx_usdhc_error_recovery()
212 /* Reset command line */ in imx_usdhc_error_recovery()
213 USDHC_Reset(cfg->base, kUSDHC_ResetCommand, 100U); in imx_usdhc_error_recovery()
216 (USDHC_GetAdmaErrorStatusFlags(cfg->base) != 0U)) { in imx_usdhc_error_recovery()
218 USDHC_Reset(cfg->base, kUSDHC_DataInhibitFlag, 100U); in imx_usdhc_error_recovery()
227 const struct usdhc_config *cfg = dev->config; in imx_usdhc_init_host_props()
228 struct usdhc_data *data = dev->data; in imx_usdhc_init_host_props()
230 struct sdhc_host_props *props = &data->props; in imx_usdhc_init_host_props()
233 props->f_max = cfg->max_bus_freq; in imx_usdhc_init_host_props()
234 props->f_min = cfg->min_bus_freq; in imx_usdhc_init_host_props()
235 props->max_current_330 = cfg->max_current_330; in imx_usdhc_init_host_props()
236 props->max_current_180 = cfg->max_current_180; in imx_usdhc_init_host_props()
237 props->power_delay = cfg->power_delay_ms; in imx_usdhc_init_host_props()
239 USDHC_GetCapability(cfg->base, &caps); in imx_usdhc_init_host_props()
240 if (cfg->no_180_vol) { in imx_usdhc_init_host_props()
241 props->host_caps.vol_180_support = false; in imx_usdhc_init_host_props()
243 props->host_caps.vol_180_support = (bool)(caps.flags & kUSDHC_SupportV180Flag); in imx_usdhc_init_host_props()
245 props->host_caps.vol_300_support = (bool)(caps.flags & kUSDHC_SupportV300Flag); in imx_usdhc_init_host_props()
246 props->host_caps.vol_330_support = (bool)(caps.flags & kUSDHC_SupportV330Flag); in imx_usdhc_init_host_props()
247 props->host_caps.suspend_res_support = (bool)(caps.flags & kUSDHC_SupportSuspendResumeFlag); in imx_usdhc_init_host_props()
248 props->host_caps.sdma_support = (bool)(caps.flags & kUSDHC_SupportDmaFlag); in imx_usdhc_init_host_props()
249 props->host_caps.high_spd_support = (bool)(caps.flags & kUSDHC_SupportHighSpeedFlag); in imx_usdhc_init_host_props()
250 props->host_caps.adma_2_support = (bool)(caps.flags & kUSDHC_SupportAdmaFlag); in imx_usdhc_init_host_props()
251 props->host_caps.max_blk_len = (bool)(caps.maxBlockLength); in imx_usdhc_init_host_props()
252 props->host_caps.ddr50_support = (bool)(caps.flags & kUSDHC_SupportDDR50Flag); in imx_usdhc_init_host_props()
253 props->host_caps.sdr104_support = (bool)(caps.flags & kUSDHC_SupportSDR104Flag); in imx_usdhc_init_host_props()
254 props->host_caps.sdr50_support = (bool)(caps.flags & kUSDHC_SupportSDR50Flag); in imx_usdhc_init_host_props()
255 props->host_caps.bus_8_bit_support = (bool)(caps.flags & kUSDHC_Support8BitFlag); in imx_usdhc_init_host_props()
256 props->host_caps.bus_4_bit_support = (bool)(caps.flags & kUSDHC_Support4BitFlag); in imx_usdhc_init_host_props()
257 props->host_caps.hs200_support = (bool)(cfg->mmc_hs200_1_8v); in imx_usdhc_init_host_props()
258 props->host_caps.hs400_support = (bool)(cfg->mmc_hs400_1_8v); in imx_usdhc_init_host_props()
266 const struct usdhc_config *cfg = dev->config; in imx_usdhc_reset()
268 imx_usdhc_select_1_8v(cfg->base, false); in imx_usdhc_reset()
269 USDHC_EnableDDRMode(cfg->base, false, 0U); in imx_usdhc_reset()
271 USDHC_EnableStandardTuning(cfg->base, 0, 0, false); in imx_usdhc_reset()
272 USDHC_EnableAutoTuning(cfg->base, false); in imx_usdhc_reset()
277 USDHC_EnableHS400Mode(cfg->base, false); in imx_usdhc_reset()
279 USDHC_EnableStrobeDLL(cfg->base, false); in imx_usdhc_reset()
282 /* Reset data/command/tuning circuit */ in imx_usdhc_reset()
283 return USDHC_Reset(cfg->base, kUSDHC_ResetAll, 1000U) == true ? 0 : -ETIMEDOUT; in imx_usdhc_reset()
291 const struct usdhc_config *cfg = dev->config; in imx_usdhc_set_io()
292 struct usdhc_data *data = dev->data; in imx_usdhc_set_io()
294 struct sdhc_io *host_io = &data->host_io; in imx_usdhc_set_io()
297 ios->bus_width, in imx_usdhc_set_io()
298 ios->clock, in imx_usdhc_set_io()
299 ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF", in imx_usdhc_set_io()
300 ios->signal_voltage == SD_VOL_1_8_V ? "1.8V" : "3.3V" in imx_usdhc_set_io()
303 if (clock_control_get_rate(cfg->clock_dev, in imx_usdhc_set_io()
304 cfg->clock_subsys, in imx_usdhc_set_io()
306 return -EINVAL; in imx_usdhc_set_io()
309 if (ios->clock && (ios->clock > data->props.f_max || ios->clock < data->props.f_min)) { in imx_usdhc_set_io()
310 return -EINVAL; in imx_usdhc_set_io()
314 if (host_io->clock != ios->clock) { in imx_usdhc_set_io()
315 if (ios->clock != 0) { in imx_usdhc_set_io()
317 bus_clk = USDHC_SetSdClock(cfg->base, src_clk_hz, ios->clock); in imx_usdhc_set_io()
320 return -ENOTSUP; in imx_usdhc_set_io()
323 host_io->clock = ios->clock; in imx_usdhc_set_io()
328 if (host_io->bus_width != ios->bus_width) { in imx_usdhc_set_io()
329 switch (ios->bus_width) { in imx_usdhc_set_io()
331 USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth1Bit); in imx_usdhc_set_io()
334 USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth4Bit); in imx_usdhc_set_io()
337 USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth8Bit); in imx_usdhc_set_io()
340 return -ENOTSUP; in imx_usdhc_set_io()
342 host_io->bus_width = ios->bus_width; in imx_usdhc_set_io()
346 if (ios->signal_voltage != host_io->signal_voltage) { in imx_usdhc_set_io()
347 switch (ios->signal_voltage) { in imx_usdhc_set_io()
350 imx_usdhc_select_1_8v(cfg->base, false); in imx_usdhc_set_io()
359 * on. We will instead delay 10 ms to allow the clock in imx_usdhc_set_io()
364 imx_usdhc_select_1_8v(cfg->base, true); in imx_usdhc_set_io()
365 /* Wait 10 ms- clock will be gated during this period */ in imx_usdhc_set_io()
368 USDHC_ForceClockOn(cfg->base, true); in imx_usdhc_set_io()
372 USDHC_ForceClockOn(cfg->base, false); in imx_usdhc_set_io()
375 return -ENOTSUP; in imx_usdhc_set_io()
378 host_io->signal_voltage = ios->signal_voltage; in imx_usdhc_set_io()
382 if ((host_io->power_mode != ios->power_mode) && (cfg->pwr_gpio.port)) { in imx_usdhc_set_io()
383 if (ios->power_mode == SDHC_POWER_OFF) { in imx_usdhc_set_io()
384 gpio_pin_set_dt(&cfg->pwr_gpio, 0); in imx_usdhc_set_io()
385 } else if (ios->power_mode == SDHC_POWER_ON) { in imx_usdhc_set_io()
386 gpio_pin_set_dt(&cfg->pwr_gpio, 1); in imx_usdhc_set_io()
388 host_io->power_mode = ios->power_mode; in imx_usdhc_set_io()
392 if (host_io->timing != ios->timing) { in imx_usdhc_set_io()
393 switch (ios->timing) { in imx_usdhc_set_io()
400 USDHC_EnableDDRMode(cfg->base, true, 0); in imx_usdhc_set_io()
404 pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_SLOW); in imx_usdhc_set_io()
407 pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_MED); in imx_usdhc_set_io()
411 USDHC_EnableHS400Mode(cfg->base, true); in imx_usdhc_set_io()
412 USDHC_EnableDDRMode(cfg->base, true, 0U); in imx_usdhc_set_io()
413 USDHC_ConfigStrobeDLL(cfg->base, 7U, 4U); in imx_usdhc_set_io()
414 USDHC_EnableStrobeDLL(cfg->base, true); in imx_usdhc_set_io()
417 return -ENOTSUP; in imx_usdhc_set_io()
421 pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_FAST); in imx_usdhc_set_io()
424 return -ENOTSUP; in imx_usdhc_set_io()
426 host_io->timing = ios->timing; in imx_usdhc_set_io()
438 const struct usdhc_config *cfg = dev->config; in imx_usdhc_transfer()
439 struct usdhc_data *dev_data = dev->data; in imx_usdhc_transfer()
445 dma_config.admaTable = dev_data->usdhc_dma_descriptor; in imx_usdhc_transfer()
446 dma_config.admaTableWords = dev_data->dma_descriptor_len; in imx_usdhc_transfer()
454 dev_data->transfer_status = 0U; in imx_usdhc_transfer()
456 k_sem_reset(&dev_data->transfer_sem); in imx_usdhc_transfer()
458 error = USDHC_TransferNonBlocking(cfg->base, &dev_data->transfer_handle, in imx_usdhc_transfer()
459 &dma_config, request->transfer); in imx_usdhc_transfer()
461 error = USDHC_TransferNonBlocking(cfg->base, &dev_data->transfer_handle, in imx_usdhc_transfer()
462 NULL, request->transfer); in imx_usdhc_transfer()
465 return -EAGAIN; in imx_usdhc_transfer()
467 return -EIO; in imx_usdhc_transfer()
470 while ((dev_data->transfer_status & (TRANSFER_CMD_FLAGS | TRANSFER_DATA_FLAGS)) == 0) { in imx_usdhc_transfer()
471 if (k_sem_take(&dev_data->transfer_sem, request->command_timeout)) { in imx_usdhc_transfer()
472 return -ETIMEDOUT; in imx_usdhc_transfer()
475 if (dev_data->transfer_status & TRANSFER_CMD_FAILED) { in imx_usdhc_transfer()
476 return -EIO; in imx_usdhc_transfer()
479 if (request->transfer->data) { in imx_usdhc_transfer()
480 while ((dev_data->transfer_status & TRANSFER_DATA_FLAGS) == 0) { in imx_usdhc_transfer()
481 if (k_sem_take(&dev_data->transfer_sem, request->data_timeout)) { in imx_usdhc_transfer()
482 return -ETIMEDOUT; in imx_usdhc_transfer()
485 if (dev_data->transfer_status & TRANSFER_DATA_FAILED) { in imx_usdhc_transfer()
486 return -EIO; in imx_usdhc_transfer()
492 /* Stops transmission after failed command with CMD12 */
504 transfer.command = &stop_cmd; in imx_usdhc_stop_transmission()
519 const struct usdhc_config *cfg = dev->config; in imx_usdhc_card_busy()
521 return (USDHC_GetPresentStatusFlags(cfg->base) in imx_usdhc_card_busy()
534 const struct usdhc_config *cfg = dev->config; in imx_usdhc_execute_tuning()
535 struct usdhc_data *dev_data = dev->data; in imx_usdhc_execute_tuning()
543 if ((dev_data->host_io.timing == SDHC_TIMING_HS200) || in imx_usdhc_execute_tuning()
544 (dev_data->host_io.timing == SDHC_TIMING_HS400)) { in imx_usdhc_execute_tuning()
553 if (dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) { in imx_usdhc_execute_tuning()
554 data.blockSize = sizeof(dev_data->usdhc_rx_dummy); in imx_usdhc_execute_tuning()
556 data.blockSize = sizeof(dev_data->usdhc_rx_dummy) / 2; in imx_usdhc_execute_tuning()
559 data.rxData = (uint32_t *)dev_data->usdhc_rx_dummy; in imx_usdhc_execute_tuning()
562 transfer.command = &cmd; in imx_usdhc_execute_tuning()
566 USDHC_Reset(cfg->base, kUSDHC_ResetTuning, 100U); in imx_usdhc_execute_tuning()
568 USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START, in imx_usdhc_execute_tuning()
570 USDHC_ForceClockOn(cfg->base, true); in imx_usdhc_execute_tuning()
572 * Tuning fail found on some SOCs is caused by the different of delay in imx_usdhc_execute_tuning()
576 USDHC_SetStandardTuningCounter(cfg->base, IMX_USDHC_STANDARD_TUNING_COUNTER); in imx_usdhc_execute_tuning()
578 USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START, in imx_usdhc_execute_tuning()
590 /* Delay 1ms */ in imx_usdhc_execute_tuning()
593 /* Wait for execute tuning bit to clear */ in imx_usdhc_execute_tuning()
594 if (USDHC_GetExecuteStdTuningStatus(cfg->base) != 0) { in imx_usdhc_execute_tuning()
598 if ((USDHC_CheckTuningError(cfg->base) != 0U) && retry_tuning) { in imx_usdhc_execute_tuning()
601 USDHC_EnableStandardTuning(cfg->base, in imx_usdhc_execute_tuning()
604 USDHC_SetTuningDelay(cfg->base, in imx_usdhc_execute_tuning()
612 if (USDHC_CheckStdTuningResult(cfg->base) == 0) { in imx_usdhc_execute_tuning()
613 return -EIO; in imx_usdhc_execute_tuning()
615 USDHC_ForceClockOn(cfg->base, false); in imx_usdhc_execute_tuning()
618 USDHC_EnableAutoTuning(cfg->base, true); in imx_usdhc_execute_tuning()
628 const struct usdhc_config *cfg = dev->config; in imx_usdhc_request()
629 struct usdhc_data *dev_data = dev->data; in imx_usdhc_request()
636 int retries = (int)cmd->retries; in imx_usdhc_request()
638 if (cmd->opcode == SD_GO_IDLE_STATE) { in imx_usdhc_request()
639 USDHC_SetCardActive(cfg->base, 0xFFFF); in imx_usdhc_request()
642 host_cmd.index = cmd->opcode; in imx_usdhc_request()
643 host_cmd.argument = cmd->arg; in imx_usdhc_request()
645 host_cmd.responseType = (cmd->response_type & SDHC_NATIVE_RESPONSE_MASK); in imx_usdhc_request()
646 transfer.command = &host_cmd; in imx_usdhc_request()
647 if (cmd->timeout_ms == SDHC_TIMEOUT_FOREVER) { in imx_usdhc_request()
650 request.command_timeout = K_MSEC(cmd->timeout_ms); in imx_usdhc_request()
654 host_data.blockSize = data->block_size; in imx_usdhc_request()
655 host_data.blockCount = data->blocks; in imx_usdhc_request()
657 * Determine type of command. Note that driver is expected to in imx_usdhc_request()
660 switch (cmd->opcode) { in imx_usdhc_request()
663 host_data.txData = data->data; in imx_usdhc_request()
666 if (dev_data->host_io.timing == SDHC_TIMING_SDR104) { in imx_usdhc_request()
673 host_data.txData = data->data; in imx_usdhc_request()
677 host_data.rxData = data->data; in imx_usdhc_request()
680 if (dev_data->host_io.timing == SDHC_TIMING_SDR104) { in imx_usdhc_request()
687 host_data.rxData = data->data; in imx_usdhc_request()
694 host_data.rxData = data->data; in imx_usdhc_request()
699 host_data.txData = data->data; in imx_usdhc_request()
701 host_data.rxData = data->data; in imx_usdhc_request()
705 return -ENOTSUP; in imx_usdhc_request()
709 if (data->timeout_ms == SDHC_TIMEOUT_FOREVER) { in imx_usdhc_request()
712 request.data_timeout = K_MSEC(data->timeout_ms); in imx_usdhc_request()
721 if (k_mutex_lock(&dev_data->access_mutex, request.command_timeout) != 0) { in imx_usdhc_request()
722 return -EBUSY; in imx_usdhc_request()
728 * Disable and clear interrupts. If the data transmission in imx_usdhc_request()
733 USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CommandFlag | in imx_usdhc_request()
735 USDHC_ClearInterruptStatusFlags(cfg->base, kUSDHC_CommandFlag | in imx_usdhc_request()
744 /* Wait 125us before polling again */ in imx_usdhc_request()
746 busy_timeout -= 125; in imx_usdhc_request()
750 k_mutex_unlock(&dev_data->access_mutex); in imx_usdhc_request()
751 return -ETIMEDOUT; in imx_usdhc_request()
754 if (ret == -EAGAIN) { in imx_usdhc_request()
756 if (dev_data->host_io.timing == SDHC_TIMING_SDR50 || in imx_usdhc_request()
757 dev_data->host_io.timing == SDHC_TIMING_SDR104 || in imx_usdhc_request()
758 dev_data->host_io.timing == SDHC_TIMING_HS200 || in imx_usdhc_request()
759 dev_data->host_io.timing == SDHC_TIMING_HS400) { in imx_usdhc_request()
765 k_mutex_unlock(&dev_data->access_mutex); in imx_usdhc_request()
772 retries--; in imx_usdhc_request()
779 k_mutex_unlock(&dev_data->access_mutex); in imx_usdhc_request()
780 /* Record command response */ in imx_usdhc_request()
781 memcpy(cmd->response, host_cmd.response, sizeof(cmd->response)); in imx_usdhc_request()
784 data->bytes_xfered = dev_data->transfer_handle.transferredWords; in imx_usdhc_request()
794 const struct usdhc_config *cfg = dev->config; in imx_usdhc_get_card_present()
795 struct usdhc_data *data = dev->data; in imx_usdhc_get_card_present()
797 if (cfg->detect_dat3) { in imx_usdhc_get_card_present()
802 if (!data->card_present) { in imx_usdhc_get_card_present()
805 USDHC_CardDetectByData3(cfg->base, true); in imx_usdhc_get_card_present()
806 /* Delay to ensure host has time to detect card */ in imx_usdhc_get_card_present()
808 data->card_present = USDHC_DetectCardInsert(cfg->base); in imx_usdhc_get_card_present()
809 /* Clear card detection and pull */ in imx_usdhc_get_card_present()
811 USDHC_CardDetectByData3(cfg->base, false); in imx_usdhc_get_card_present()
813 } else if (cfg->detect_cd) { in imx_usdhc_get_card_present()
818 data->card_present = USDHC_DetectCardInsert(cfg->base); in imx_usdhc_get_card_present()
819 } else if (cfg->detect_gpio.port) { in imx_usdhc_get_card_present()
820 data->card_present = gpio_pin_get_dt(&cfg->detect_gpio) > 0; in imx_usdhc_get_card_present()
824 data->card_present = true; in imx_usdhc_get_card_present()
826 return ((int)data->card_present); in imx_usdhc_get_card_present()
835 struct usdhc_data *data = dev->data; in imx_usdhc_get_host_props()
837 memcpy(props, &data->props, sizeof(struct sdhc_host_props)); in imx_usdhc_get_host_props()
848 const struct usdhc_config *cfg = dev->config; in imx_usdhc_enable_interrupt()
849 struct usdhc_data *data = dev->data; in imx_usdhc_enable_interrupt()
853 data->sdhc_cb = callback; in imx_usdhc_enable_interrupt()
854 data->sdhc_cb_user_data = user_data; in imx_usdhc_enable_interrupt()
857 USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInterruptFlag); in imx_usdhc_enable_interrupt()
858 USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInterruptFlag); in imx_usdhc_enable_interrupt()
859 if (cfg->detect_gpio.port) { in imx_usdhc_enable_interrupt()
860 ret = gpio_pin_interrupt_configure_dt(&cfg->detect_gpio, in imx_usdhc_enable_interrupt()
866 USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInsertionFlag); in imx_usdhc_enable_interrupt()
867 USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInsertionFlag); in imx_usdhc_enable_interrupt()
868 USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardRemovalFlag); in imx_usdhc_enable_interrupt()
869 USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardRemovalFlag); in imx_usdhc_enable_interrupt()
874 USDHC_EnableInterruptStatus(cfg->base, kUSDHC_CardInterruptFlag); in imx_usdhc_enable_interrupt()
875 USDHC_EnableInterruptSignal(cfg->base, kUSDHC_CardInterruptFlag); in imx_usdhc_enable_interrupt()
878 if (cfg->detect_gpio.port) { in imx_usdhc_enable_interrupt()
880 ret = gpio_pin_interrupt_configure_dt(&cfg->detect_gpio, in imx_usdhc_enable_interrupt()
887 USDHC_EnableInterruptStatus(cfg->base, in imx_usdhc_enable_interrupt()
889 USDHC_EnableInterruptSignal(cfg->base, in imx_usdhc_enable_interrupt()
894 if (cfg->detect_gpio.port) { in imx_usdhc_enable_interrupt()
896 ret = gpio_pin_interrupt_configure_dt(&cfg->detect_gpio, in imx_usdhc_enable_interrupt()
903 USDHC_EnableInterruptStatus(cfg->base, in imx_usdhc_enable_interrupt()
905 USDHC_EnableInterruptSignal(cfg->base, in imx_usdhc_enable_interrupt()
915 const struct usdhc_config *cfg = dev->config; in imx_usdhc_disable_interrupt()
916 struct usdhc_data *data = dev->data; in imx_usdhc_disable_interrupt()
922 USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInterruptFlag); in imx_usdhc_disable_interrupt()
923 USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInterruptFlag); in imx_usdhc_disable_interrupt()
926 if (cfg->detect_gpio.port) { in imx_usdhc_disable_interrupt()
927 ret = gpio_pin_interrupt_configure_dt(&cfg->detect_gpio, in imx_usdhc_disable_interrupt()
934 USDHC_DisableInterruptStatus(cfg->base, in imx_usdhc_disable_interrupt()
936 USDHC_DisableInterruptSignal(cfg->base, in imx_usdhc_disable_interrupt()
941 if (cfg->detect_gpio.port) { in imx_usdhc_disable_interrupt()
942 ret = gpio_pin_interrupt_configure_dt(&cfg->detect_gpio, in imx_usdhc_disable_interrupt()
949 USDHC_DisableInterruptStatus(cfg->base, in imx_usdhc_disable_interrupt()
951 USDHC_DisableInterruptSignal(cfg->base, in imx_usdhc_disable_interrupt()
957 if ((USDHC_GetEnabledInterruptStatusFlags(cfg->base) & in imx_usdhc_disable_interrupt()
960 data->sdhc_cb = NULL; in imx_usdhc_disable_interrupt()
961 data->sdhc_cb_user_data = NULL; in imx_usdhc_disable_interrupt()
969 const struct usdhc_config *cfg = dev->config; in imx_usdhc_isr()
970 struct usdhc_data *data = dev->data; in imx_usdhc_isr()
972 USDHC_TransferHandleIRQ(cfg->base, &data->transfer_handle); in imx_usdhc_isr()
981 const struct usdhc_config *cfg = dev->config; in imx_usdhc_init()
982 struct usdhc_data *data = dev->data; in imx_usdhc_init()
992 if (!device_is_ready(cfg->clock_dev)) { in imx_usdhc_init()
994 return -ENODEV; in imx_usdhc_init()
997 ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); in imx_usdhc_init()
1001 USDHC_TransferCreateHandle(cfg->base, &data->transfer_handle, in imx_usdhc_init()
1003 cfg->irq_config_func(dev); in imx_usdhc_init()
1006 host_config.dataTimeout = cfg->data_timeout; in imx_usdhc_init()
1008 host_config.readWatermarkLevel = cfg->read_watermark; in imx_usdhc_init()
1009 host_config.writeWatermarkLevel = cfg->write_watermark; in imx_usdhc_init()
1010 USDHC_Init(cfg->base, &host_config); in imx_usdhc_init()
1014 if (cfg->pwr_gpio.port) { in imx_usdhc_init()
1015 ret = gpio_pin_configure_dt(&cfg->pwr_gpio, GPIO_OUTPUT_INACTIVE); in imx_usdhc_init()
1023 if (cfg->detect_gpio.port) { in imx_usdhc_init()
1024 ret = gpio_pin_configure_dt(&cfg->detect_gpio, GPIO_INPUT); in imx_usdhc_init()
1028 gpio_init_callback(&data->cd_callback, card_detect_gpio_cb, in imx_usdhc_init()
1029 BIT(cfg->detect_gpio.pin)); in imx_usdhc_init()
1030 ret = gpio_add_callback_dt(&cfg->detect_gpio, &data->cd_callback); in imx_usdhc_init()
1035 data->dev = dev; in imx_usdhc_init()
1036 k_mutex_init(&data->access_mutex); in imx_usdhc_init()
1038 data->host_io.clock = 0; in imx_usdhc_init()
1039 data->host_io.bus_mode = SDHC_BUSMODE_PUSHPULL; in imx_usdhc_init()
1040 data->host_io.power_mode = SDHC_POWER_OFF; in imx_usdhc_init()
1041 data->host_io.bus_width = SDHC_BUS_WIDTH1BIT; in imx_usdhc_init()
1042 data->host_io.timing = SDHC_TIMING_LEGACY; in imx_usdhc_init()
1043 data->host_io.driver_type = SD_DRIVER_TYPE_B; in imx_usdhc_init()
1044 data->host_io.signal_voltage = SD_VOL_3_3_V; in imx_usdhc_init()
1046 return k_sem_init(&data->transfer_sem, 0, 1); in imx_usdhc_init()