Lines Matching +full:pwm +full:- +full:output +full:- +full:frequency

4  * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
30 "Only clock-prescaler = <0> is supported when used with RTC");
39 /* One compare channel is needed to set the PWM period, hence +1. */
41 #error "Invalid number of PWM channels configured."
82 return config->rtc; in pwm_config_rtc()
91 return config->timer; in pwm_config_timer()
103 /* allow 0% and 100% duty cycle, as it does not use PWM. */ in pwm_period_check()
111 (data->pulse_cycles[i] != 0U) && in pwm_period_check()
112 (period_cycles != data->period_cycles)) { in pwm_period_check()
113 return -EINVAL; in pwm_period_check()
124 const struct pwm_config *config = dev->config; in pwm_nrf_sw_set_cycles()
128 struct pwm_data *data = dev->data; in pwm_nrf_sw_set_cycles()
136 if (channel >= config->map_size) { in pwm_nrf_sw_set_cycles()
138 return -EINVAL; in pwm_nrf_sw_set_cycles()
144 ret = pwm_period_check(data, config->map_size, channel, period_cycles, in pwm_nrf_sw_set_cycles()
152 /* pulse_cycles - 1 is written to 24-bit CC */ in pwm_nrf_sw_set_cycles()
155 return -EINVAL; in pwm_nrf_sw_set_cycles()
160 LOG_ERR("Too long period (%u), adjust PWM prescaler!", in pwm_nrf_sw_set_cycles()
162 return -EINVAL; in pwm_nrf_sw_set_cycles()
166 gpiote = config->gpiote[channel].p_reg; in pwm_nrf_sw_set_cycles()
167 psel_ch = config->psel_ch[channel]; in pwm_nrf_sw_set_cycles()
168 gpiote_ch = data->gpiote_ch[channel]; in pwm_nrf_sw_set_cycles()
169 ppi_chs = data->ppi_ch[channel]; in pwm_nrf_sw_set_cycles()
183 * the PWM signal, just keep the output pin in inactive or active in pwm_nrf_sw_set_cycles()
194 /* No PWM generation for this channel. */ in pwm_nrf_sw_set_cycles()
195 data->pulse_cycles[channel] = 0U; in pwm_nrf_sw_set_cycles()
197 /* Check if PWM signal is generated on any channel. */ in pwm_nrf_sw_set_cycles()
198 for (uint8_t i = 0; i < config->map_size; i++) { in pwm_nrf_sw_set_cycles()
199 if (data->pulse_cycles[i]) { in pwm_nrf_sw_set_cycles()
204 /* No PWM generation needed, stop the timer. */ in pwm_nrf_sw_set_cycles()
222 * '- 1' adjusts pulse and period cycles to the fact that CLEAR in pwm_nrf_sw_set_cycles()
226 nrf_rtc_cc_set(rtc, 1 + channel, pulse_cycles - 1); in pwm_nrf_sw_set_cycles()
227 nrf_rtc_cc_set(rtc, 0, period_cycles - 1); in pwm_nrf_sw_set_cycles()
240 /* Configure GPIOTE - toggle task with proper initial output value. */ in pwm_nrf_sw_set_cycles()
241 gpiote->CONFIG[gpiote_ch] = in pwm_nrf_sw_set_cycles()
302 /* start timer, hence PWM */ in pwm_nrf_sw_set_cycles()
310 data->period_cycles = period_cycles; in pwm_nrf_sw_set_cycles()
311 data->pulse_cycles[channel] = pulse_cycles; in pwm_nrf_sw_set_cycles()
319 const struct pwm_config *config = dev->config; in pwm_nrf_sw_get_cycles_per_sec()
323 * RTC frequency is derived from 32768Hz source without any in pwm_nrf_sw_get_cycles_per_sec()
329 * HF timer frequency is derived from 16MHz source with a in pwm_nrf_sw_get_cycles_per_sec()
332 *cycles = 16000000UL / BIT(config->prescaler); in pwm_nrf_sw_get_cycles_per_sec()
338 static DEVICE_API(pwm, pwm_nrf_sw_drv_api_funcs) = {
345 const struct pwm_config *config = dev->config; in pwm_nrf_sw_init()
346 struct pwm_data *data = dev->data; in pwm_nrf_sw_init()
350 for (uint32_t i = 0; i < config->map_size; i++) { in pwm_nrf_sw_init()
355 err = nrfx_gppi_channel_alloc(&data->ppi_ch[i][j]); in pwm_nrf_sw_init()
361 return -ENOMEM; in pwm_nrf_sw_init()
365 err = nrfx_gpiote_channel_alloc(&config->gpiote[i], in pwm_nrf_sw_init()
366 &data->gpiote_ch[i]); in pwm_nrf_sw_init()
372 return -ENOMEM; in pwm_nrf_sw_init()
375 /* Set initial state of the output pins. */ in pwm_nrf_sw_init()
376 nrf_gpio_pin_write(config->psel_ch[i], in pwm_nrf_sw_init()
377 (config->initially_inverted & BIT(i)) ? 1 : 0); in pwm_nrf_sw_init()
378 nrf_gpio_cfg_output(config->psel_ch[i]); in pwm_nrf_sw_init()
391 nrf_timer_prescaler_set(timer, config->prescaler); in pwm_nrf_sw_init()