4  * SPDX-License-Identifier: Apache-2.0
39 	const struct pwm_mcux_qtmr_config *config = dev->config;  in mcux_qtmr_pwm_set_cycles()
40 	struct pwm_mcux_qtmr_data *data = dev->data;  in mcux_qtmr_pwm_set_cycles()
46 		return -EINVAL;  in mcux_qtmr_pwm_set_cycles()
52 	lowCount = period_cycles - pulse_cycles;  in mcux_qtmr_pwm_set_cycles()
55 		highCount -= 1U;  in mcux_qtmr_pwm_set_cycles()
58 		lowCount -= 1U;  in mcux_qtmr_pwm_set_cycles()
62 		/* This should not be a 16-bit overflow value. If it is, change to a larger divider  in mcux_qtmr_pwm_set_cycles()
65 		return -EINVAL;  in mcux_qtmr_pwm_set_cycles()
68 	k_mutex_lock(&data->lock, K_FOREVER);  in mcux_qtmr_pwm_set_cycles()
71 	config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);  in mcux_qtmr_pwm_set_cycles()
73 	QTMR_StopTimer(config->base, channel);  in mcux_qtmr_pwm_set_cycles()
76 	config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount;  in mcux_qtmr_pwm_set_cycles()
77 	config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount;  in mcux_qtmr_pwm_set_cycles()
79 	/* Setup the pre-load registers for PWM output */  in mcux_qtmr_pwm_set_cycles()
80 	config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount;  in mcux_qtmr_pwm_set_cycles()
81 	config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount;  in mcux_qtmr_pwm_set_cycles()
83 	reg = config->base->CHANNEL[channel].CSCTRL;  in mcux_qtmr_pwm_set_cycles()
84 	/* Setup the compare load control for COMP1 and COMP2.  in mcux_qtmr_pwm_set_cycles()
89 	config->base->CHANNEL[channel].CSCTRL = reg;  in mcux_qtmr_pwm_set_cycles()
91 	reg = config->base->CHANNEL[channel].CTRL;  in mcux_qtmr_pwm_set_cycles()
104 	config->base->CHANNEL[channel].CTRL = reg;  in mcux_qtmr_pwm_set_cycles()
106 	QTMR_StartTimer(config->base, channel, kQTMR_PriSrcRiseEdge);  in mcux_qtmr_pwm_set_cycles()
108 	k_mutex_unlock(&data->lock);  in mcux_qtmr_pwm_set_cycles()
116 	const struct pwm_mcux_qtmr_config *config = dev->config;  in mcux_qtmr_pwm_get_cycles_per_sec()
119 	if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) {  in mcux_qtmr_pwm_get_cycles_per_sec()
120 		return -EINVAL;  in mcux_qtmr_pwm_get_cycles_per_sec()
123 	*cycles = clock_freq / config->prescaler;  in mcux_qtmr_pwm_get_cycles_per_sec()
130 	const struct pwm_mcux_qtmr_config *config = dev->config;  in mcux_qtmr_pwm_init()
131 	struct pwm_mcux_qtmr_data *data = dev->data;  in mcux_qtmr_pwm_init()
135 	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);  in mcux_qtmr_pwm_init()
140 	k_mutex_init(&data->lock);  in mcux_qtmr_pwm_init()
143 	qtmr_config.primarySource = kQTMR_ClockDivide_1 + (31 - __builtin_clz(config->prescaler));  in mcux_qtmr_pwm_init()
146 		QTMR_Init(config->base, i, &qtmr_config);  in mcux_qtmr_pwm_init()