4  * SPDX-License-Identifier: Apache-2.0
36 	/** Flag to indicate if timer has 32-bit counter */
50 /** Obtain channel enable bit for the given channel */
52 /** Obtain polarity bit for the given channel */
54 /** Obtain CHCTL0/1 mask for the given channel (0 or 1) */
60 static int pwm_gd32_set_cycles(const struct device *dev, uint32_t channel,  in pwm_gd32_set_cycles()  argument
64 	const struct pwm_gd32_config *config = dev->config;  in pwm_gd32_set_cycles()
66 	if (channel >= config->channels) {  in pwm_gd32_set_cycles()
67 		return -EINVAL;  in pwm_gd32_set_cycles()
70 	/* 16-bit timers can count up to UINT16_MAX */  in pwm_gd32_set_cycles()
71 	if (!config->is_32bit && (period_cycles > UINT16_MAX)) {  in pwm_gd32_set_cycles()
72 		return -ENOTSUP;  in pwm_gd32_set_cycles()
75 	/* disable channel output if period is zero */  in pwm_gd32_set_cycles()
77 		TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(channel);  in pwm_gd32_set_cycles()
83 		TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXP(channel);  in pwm_gd32_set_cycles()
85 		TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXP(channel);  in pwm_gd32_set_cycles()
89 	switch (channel) {  in pwm_gd32_set_cycles()
91 		TIMER_CH0CV(config->reg) = pulse_cycles;  in pwm_gd32_set_cycles()
94 		TIMER_CH1CV(config->reg) = pulse_cycles;  in pwm_gd32_set_cycles()
97 		TIMER_CH2CV(config->reg) = pulse_cycles;  in pwm_gd32_set_cycles()
100 		TIMER_CH3CV(config->reg) = pulse_cycles;  in pwm_gd32_set_cycles()
108 	TIMER_CAR(config->reg) = period_cycles;  in pwm_gd32_set_cycles()
110 	/* channel not enabled: configure it */  in pwm_gd32_set_cycles()
111 	if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(channel)) == 0U) {  in pwm_gd32_set_cycles()
114 		/* select PWM1 mode, enable OC shadowing */  in pwm_gd32_set_cycles()
115 		if (channel < 2U) {  in pwm_gd32_set_cycles()
116 			chctl = &TIMER_CHCTL0(config->reg);  in pwm_gd32_set_cycles()
118 			chctl = &TIMER_CHCTL1(config->reg);  in pwm_gd32_set_cycles()
121 		*chctl &= ~TIMER_CHCTLX_MSK(channel);  in pwm_gd32_set_cycles()
123 			  (8U * (channel % 2U));  in pwm_gd32_set_cycles()
125 		/* enable channel output */  in pwm_gd32_set_cycles()
126 		TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXEN(channel);  in pwm_gd32_set_cycles()
129 		TIMER_SWEVG(config->reg) |= TIMER_SWEVG_UPG;  in pwm_gd32_set_cycles()
136 				       uint32_t channel, uint64_t *cycles)  in pwm_gd32_get_cycles_per_sec()  argument
138 	struct pwm_gd32_data *data = dev->data;  in pwm_gd32_get_cycles_per_sec()
139 	const struct pwm_gd32_config *config = dev->config;  in pwm_gd32_get_cycles_per_sec()
141 	*cycles = (uint64_t)(data->tim_clk / (config->prescaler + 1U));  in pwm_gd32_get_cycles_per_sec()
153 	const struct pwm_gd32_config *config = dev->config;  in pwm_gd32_init()
154 	struct pwm_gd32_data *data = dev->data;  in pwm_gd32_init()
158 			       (clock_control_subsys_t)&config->clkid);  in pwm_gd32_init()
160 	(void)reset_line_toggle_dt(&config->reset);  in pwm_gd32_init()
163 	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);  in pwm_gd32_init()
170 				     (clock_control_subsys_t)&config->clkid,  in pwm_gd32_init()
171 				     &data->tim_clk);  in pwm_gd32_init()
174 	TIMER_CTL0(config->reg) = TIMER_CKDIV_DIV1 | TIMER_COUNTER_EDGE |  in pwm_gd32_init()
176 	TIMER_PSC(config->reg) = config->prescaler;  in pwm_gd32_init()
178 	/* enable primary output for advanced timers */  in pwm_gd32_init()
179 	if (config->is_advanced) {  in pwm_gd32_init()
180 		TIMER_CCHP(config->reg) |= TIMER_CCHP_POEN;  in pwm_gd32_init()
183 	/* enable timer counter */  in pwm_gd32_init()
184 	TIMER_CTL0(config->reg) |= TIMER_CTL0_CEN;  in pwm_gd32_init()