Lines Matching refs:gpt_base
40 const uint32_t gpt_base; /* GPT register base address */ member
52 HWREG(config->gpt_base + prescale_register) = prescaleValue; in write_value()
55 HWREG(config->gpt_base + value_register) = value & 0xffff; in write_value()
64 TimerDisable(config->gpt_base, TIMER_B); in set_period_and_pulse()
91 TimerEnable(config->gpt_base, TIMER_B); in set_period_and_pulse()
108 HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBPWML_INVERTED; in set_cycles()
110 HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBPWML_NORMAL; in set_cycles()
139 switch (config->gpt_base) { in get_timer_inst_number()
155 switch (config->gpt_base) { in get_timer_peripheral()
214 TimerDisable(config->gpt_base, TIMER_B); in init_pwm()
216 HWREG(config->gpt_base + GPT_O_CFG) = GPT_CFG_CFG_16BIT_TIMER; in init_pwm()
221 HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBSTALL; in init_pwm()
223 HWREG(config->gpt_base + GPT_O_TBMR) = GPT_TBMR_TBAMS_PWM | GPT_TBMR_TBMRSU_TOUPDATE | in init_pwm()
238 .gpt_base = DT_TIMER_BASE_ADDR(idx), \