71 	WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1);  in pinctrl_eos_s3_configure_pin()
74 	WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable);  in pinctrl_eos_s3_configure_pin()
75 	WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate);  in pinctrl_eos_s3_configure_pin()
76 	WRITE_BIT(reg_value, PAD_SCHMITT_EN_BIT, pin->schmitt_enable);  in pinctrl_eos_s3_configure_pin()
77 	WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT0, pin->control_selection & BIT(0));  in pinctrl_eos_s3_configure_pin()
78 	WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT1, pin->control_selection & BIT(1));  in pinctrl_eos_s3_configure_pin()
82 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0);  in pinctrl_eos_s3_configure_pin()
83 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0);  in pinctrl_eos_s3_configure_pin()
86 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1);  in pinctrl_eos_s3_configure_pin()
87 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0);  in pinctrl_eos_s3_configure_pin()
90 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0);  in pinctrl_eos_s3_configure_pin()
91 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1);  in pinctrl_eos_s3_configure_pin()
94 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1);  in pinctrl_eos_s3_configure_pin()
95 		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1);  in pinctrl_eos_s3_configure_pin()
102 	WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 1);  in pinctrl_eos_s3_configure_pin()
103 	WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, 0);  in pinctrl_eos_s3_configure_pin()
105 		WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 0);  in pinctrl_eos_s3_configure_pin()
107 		WRITE_BIT(reg_value, PAD_PULL_UP_BIT, pin->pull_up);  in pinctrl_eos_s3_configure_pin()
108 		WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, pin->pull_down);  in pinctrl_eos_s3_configure_pin()