Lines Matching +full:0 +full:x26
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \
30 * pin_mux: PORT_A[0-3]
32 * pin_mux + 2: PORT_B[0-3]
34 * pin_mux + 4: PORT_C[0-3]
36 * pin_mux + 6: PORT_D[0-3]
38 * pin_mux + 0x20: PORT_E[0-3]
39 * pin_mux + 0x21: PORT_E[4-7]
40 * pin_mux + 0x26: PORT_F[0-3]
41 * pin_mux + 0x27: PORT_F[4-7]
43 #define reg_pin_mux(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, pin_mux) + \
44 (((pin >> 8) < 4) ? ((pin >> 8) * 2) : 0) + \
45 (((pin >> 8) == 4) ? 0x20 : 0) + \
46 (((pin >> 8) == 5) ? 0x26 : 0) + \
47 ((pin & 0x0f0) ? 1 : 0)))
52 * pull_up_en: PORT_A[0-3]
54 * pull_up_en + 2: PORT_B[0-3]
56 * pull_up_en + 4: PORT_C[0-3]
58 * pull_up_en + 6: PORT_D[0-3]
60 * pull_up_en + 8: PORT_E[0-3]
62 * pull_up_en + 10: PORT_F[0-3]
65 #define reg_pull_up_en(pin) ((uint8_t)(DT_INST_REG_ADDR_BY_NAME(0, pull_up_en) + \
67 ((pin & 0xf0) ? 1 : 0)))
74 reg_gpio_pad_mul_sel |= DT_INST_PROP(0, pad_mul_sel); in pinctrl_b91_init()
76 return 0; in pinctrl_b91_init()
84 uint8_t bit = pin & 0xff; in pinctrl_b91_gpio_function_disable()
122 return 0; in pinctrl_b91_get_offset()
130 uint8_t offset = 0; in pinctrl_configure_pin()
138 if (status != 0) { in pinctrl_configure_pin()
162 int status = 0; in pinctrl_configure_pins()
164 for (uint8_t i = 0; i < pin_cnt; i++) { in pinctrl_configure_pins()
166 if (status < 0) { in pinctrl_configure_pins()