47 	struct peci_regs * const regs;  member
132 static int check_bus_idle(struct peci_regs * const regs)  in check_bus_idle()  argument
140 	while (!(regs->STATUS2 & MCHP_PECI_STS2_IDLE)) {  in check_bus_idle()
156 	struct peci_regs * const regs = cfg->regs;  in peci_xec_configure()  local
162 	regs->CONTROL = MCHP_PECI_CTRL_PD;  in peci_xec_configure()
166 	regs->OPT_BIT_TIME_LSB = value & MCHP_PECI_OPT_BT_LSB_MASK;  in peci_xec_configure()
167 	regs->OPT_BIT_TIME_MSB = ((value >> OPT_BIT_TIME_MSB_OFS) &  in peci_xec_configure()
171 	regs->CONTROL &= ~MCHP_PECI_CTRL_PD;  in peci_xec_configure()
179 	struct peci_regs * const regs = cfg->regs;  in peci_xec_disable()  local
183 	ret = check_bus_idle(regs);  in peci_xec_disable()
193 	regs->CONTROL |= MCHP_PECI_CTRL_PD;  in peci_xec_disable()
201 	struct peci_regs * const regs = cfg->regs;  in peci_xec_enable()  local
203 	regs->CONTROL &= ~MCHP_PECI_CTRL_PD;  in peci_xec_enable()
217 	struct peci_regs * const regs = cfg->regs;  in peci_xec_bus_recovery()  local
221 		regs->CONTROL = MCHP_PECI_CTRL_PD | MCHP_PECI_CTRL_RST;  in peci_xec_bus_recovery()
229 		regs->CONTROL &= ~MCHP_PECI_CTRL_RST;  in peci_xec_bus_recovery()
234 		regs->CONTROL |= MCHP_PECI_CTRL_FRST;  in peci_xec_bus_recovery()
242 	struct peci_regs * const regs = cfg->regs;  in peci_xec_write()  local
250 	if (regs->STATUS2 & MCHP_PECI_STS2_WFF) {  in peci_xec_write()
255 	regs->CONTROL &= ~MCHP_PECI_CTRL_FRST;  in peci_xec_write()
258 	regs->WR_DATA = msg->addr;  in peci_xec_write()
259 	regs->WR_DATA = tx_buf->len;  in peci_xec_write()
260 	regs->WR_DATA = rx_buf->len;  in peci_xec_write()
264 		regs->WR_DATA = msg->cmd_code;  in peci_xec_write()
266 			if (!(regs->STATUS2 & MCHP_PECI_STS2_WFF)) {  in peci_xec_write()
267 				regs->WR_DATA = tx_buf->buf[i];  in peci_xec_write()
273 	ret = check_bus_idle(regs);  in peci_xec_write()
278 	regs->CONTROL |= MCHP_PECI_CTRL_TXEN;  in peci_xec_write()
290 	while (!(regs->STATUS1 & MCHP_PECI_STS1_EOF)) {  in peci_xec_write()
315 	struct peci_regs * const regs = cfg->regs;  in peci_xec_read()  local
329 		while (regs->STATUS2 & MCHP_PECI_STS2_RFE) {  in peci_xec_read()
340 			tx_fcs = regs->RD_DATA;  in peci_xec_read()
350 			rx_buf->buf[i-1] = regs->RD_DATA;  in peci_xec_read()
353 			rx_buf->buf[i-1] = regs->RD_DATA;  in peci_xec_read()
366 	ret = check_bus_idle(regs);  in peci_xec_read()
377 	struct peci_regs * const regs = cfg->regs;  in peci_xec_transfer()  local
404 		if (regs->STATUS1 & MCHP_PECI_STS1_EOF) {  in peci_xec_transfer()
405 			regs->STATUS1 |= MCHP_PECI_STS1_EOF;  in peci_xec_transfer()
409 		err_val = regs->ERROR;  in peci_xec_transfer()
424 			LOG_DBG("PECI sts1 %x", regs->STATUS1);  in peci_xec_transfer()
425 			LOG_DBG("PECI sts2 %x", regs->STATUS2);  in peci_xec_transfer()
431 			regs->ERROR = err_val;  in peci_xec_transfer()
448 	struct peci_regs * const regs = devcfg->regs;  in peci_xec_pm_action()  local
459 		regs->CONTROL &= ~MCHP_PECI_CTRL_PD;  in peci_xec_pm_action()
462 		regs->CONTROL |= MCHP_PECI_CTRL_PD;  in peci_xec_pm_action()
490 	struct peci_regs * const regs = cfg->regs;  in peci_xec_isr()  local
491 	uint8_t peci_error = regs->ERROR;  in peci_xec_isr()
492 	uint8_t peci_status2 = regs->STATUS2;  in peci_xec_isr()
497 		regs->ERROR = peci_error;  in peci_xec_isr()
521 	struct peci_regs * const regs = cfg->regs;  in peci_xec_init()  local
540 	regs->CONTROL |= MCHP_PECI_CTRL_RST;  in peci_xec_init()
542 	regs->CONTROL &= ~MCHP_PECI_CTRL_RST;  in peci_xec_init()
546 	regs->INT_EN1 = (MCHP_PECI_IEN1_EREN | MCHP_PECI_IEN1_EIEN);  in peci_xec_init()
549 	regs->INT_EN2 |= MCHP_PECI_IEN2_ENWFE;  in peci_xec_init()
551 	regs->INT_EN2 |= MCHP_PECI_IEN2_ENRFF;  in peci_xec_init()
553 	regs->CONTROL |= MCHP_PECI_CTRL_MIEN;  in peci_xec_init()
568 	.regs = (struct peci_regs * const)(DT_INST_REG_ADDR(0)),