Lines Matching +full:1275 +full:- +full:1994
4 * SPDX-License-Identifier: Apache-2.0
24 * - handle prefetchable regions
47 const struct pcie_ctrl_config *cfg = dev->config; in pcie_ecam_init()
48 struct pcie_ecam_data *data = dev->data; in pcie_ecam_init()
52 * Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 : in pcie_ecam_init()
64 * t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory), in pcie_ecam_init()
69 * 10 denotes 32-bit-address Memory Space in pcie_ecam_init()
70 * 11 denotes 64-bit-address Memory Space in pcie_ecam_init()
71 * bbbbbbbb is the 8-bit Bus Number in pcie_ecam_init()
72 * ddddd is the 5-bit Device Number in pcie_ecam_init()
73 * fff is the 3-bit Function Number in pcie_ecam_init()
74 * rrrrrrrr is the 8-bit Register Number in pcie_ecam_init()
75 * hh...hh is a 32-bit unsigned number in pcie_ecam_init()
76 * ll...ll is a 32-bit unsigned number in pcie_ecam_init()
77 * for I/O Space is the 32-bit offset from the start of the region in pcie_ecam_init()
78 * for 32-bit-address Memory Space is the 32-bit offset from the start of the region in pcie_ecam_init()
79 * for 64-bit-address Memory Space is the 64-bit offset from the start of the region in pcie_ecam_init()
84 * - handle prefetchable bit in pcie_ecam_init()
86 for (i = 0 ; i < cfg->ranges_count ; ++i) { in pcie_ecam_init()
87 switch ((cfg->ranges[i].flags >> 24) & 0x03) { in pcie_ecam_init()
89 data->regions[PCIE_REGION_IO].bus_start = cfg->ranges[i].pcie_bus_addr; in pcie_ecam_init()
90 data->regions[PCIE_REGION_IO].phys_start = cfg->ranges[i].host_map_addr; in pcie_ecam_init()
91 data->regions[PCIE_REGION_IO].size = cfg->ranges[i].map_length; in pcie_ecam_init()
92 /* Linux & U-Boot avoids allocating PCI resources from address 0 */ in pcie_ecam_init()
93 if (data->regions[PCIE_REGION_IO].bus_start < 0x1000) { in pcie_ecam_init()
94 data->regions[PCIE_REGION_IO].allocation_offset = 0x1000; in pcie_ecam_init()
98 data->regions[PCIE_REGION_MEM].bus_start = cfg->ranges[i].pcie_bus_addr; in pcie_ecam_init()
99 data->regions[PCIE_REGION_MEM].phys_start = cfg->ranges[i].host_map_addr; in pcie_ecam_init()
100 data->regions[PCIE_REGION_MEM].size = cfg->ranges[i].map_length; in pcie_ecam_init()
101 /* Linux & U-Boot avoids allocating PCI resources from address 0 */ in pcie_ecam_init()
102 if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000) { in pcie_ecam_init()
103 data->regions[PCIE_REGION_MEM].allocation_offset = 0x1000; in pcie_ecam_init()
107 data->regions[PCIE_REGION_MEM64].bus_start = cfg->ranges[i].pcie_bus_addr; in pcie_ecam_init()
108 data->regions[PCIE_REGION_MEM64].phys_start = cfg->ranges[i].host_map_addr; in pcie_ecam_init()
109 data->regions[PCIE_REGION_MEM64].size = cfg->ranges[i].map_length; in pcie_ecam_init()
110 /* Linux & U-Boot avoids allocating PCI resources from address 0 */ in pcie_ecam_init()
111 if (data->regions[PCIE_REGION_MEM64].bus_start < 0x1000) { in pcie_ecam_init()
112 data->regions[PCIE_REGION_MEM64].allocation_offset = 0x1000; in pcie_ecam_init()
118 if (!data->regions[PCIE_REGION_IO].size && in pcie_ecam_init()
119 !data->regions[PCIE_REGION_MEM].size && in pcie_ecam_init()
120 !data->regions[PCIE_REGION_MEM64].size) { in pcie_ecam_init()
122 return -EINVAL; in pcie_ecam_init()
126 data->cfg_phys_addr = cfg->cfg_addr; in pcie_ecam_init()
127 data->cfg_size = cfg->cfg_size; in pcie_ecam_init()
129 if (data->regions[PCIE_REGION_IO].size) { in pcie_ecam_init()
130 LOG_DBG("IO bus [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
131 data->regions[PCIE_REGION_IO].bus_start, in pcie_ecam_init()
132 (data->regions[PCIE_REGION_IO].bus_start + in pcie_ecam_init()
133 data->regions[PCIE_REGION_IO].size - 1), in pcie_ecam_init()
134 data->regions[PCIE_REGION_IO].size); in pcie_ecam_init()
135 LOG_DBG("IO space [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
136 data->regions[PCIE_REGION_IO].phys_start, in pcie_ecam_init()
137 (data->regions[PCIE_REGION_IO].phys_start + in pcie_ecam_init()
138 data->regions[PCIE_REGION_IO].size - 1), in pcie_ecam_init()
139 data->regions[PCIE_REGION_IO].size); in pcie_ecam_init()
141 if (data->regions[PCIE_REGION_MEM].size) { in pcie_ecam_init()
142 LOG_DBG("MEM bus [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
143 data->regions[PCIE_REGION_MEM].bus_start, in pcie_ecam_init()
144 (data->regions[PCIE_REGION_MEM].bus_start + in pcie_ecam_init()
145 data->regions[PCIE_REGION_MEM].size - 1), in pcie_ecam_init()
146 data->regions[PCIE_REGION_MEM].size); in pcie_ecam_init()
147 LOG_DBG("MEM space [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
148 data->regions[PCIE_REGION_MEM].phys_start, in pcie_ecam_init()
149 (data->regions[PCIE_REGION_MEM].phys_start + in pcie_ecam_init()
150 data->regions[PCIE_REGION_MEM].size - 1), in pcie_ecam_init()
151 data->regions[PCIE_REGION_MEM].size); in pcie_ecam_init()
153 if (data->regions[PCIE_REGION_MEM64].size) { in pcie_ecam_init()
154 LOG_DBG("MEM64 bus [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
155 data->regions[PCIE_REGION_MEM64].bus_start, in pcie_ecam_init()
156 (data->regions[PCIE_REGION_MEM64].bus_start + in pcie_ecam_init()
157 data->regions[PCIE_REGION_MEM64].size - 1), in pcie_ecam_init()
158 data->regions[PCIE_REGION_MEM64].size); in pcie_ecam_init()
159 LOG_DBG("MEM64 space [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
160 data->regions[PCIE_REGION_MEM64].phys_start, in pcie_ecam_init()
161 (data->regions[PCIE_REGION_MEM64].phys_start + in pcie_ecam_init()
162 data->regions[PCIE_REGION_MEM64].size - 1), in pcie_ecam_init()
163 data->regions[PCIE_REGION_MEM64].size); in pcie_ecam_init()
167 device_map(&data->cfg_addr, data->cfg_phys_addr, data->cfg_size, K_MEM_CACHE_NONE); in pcie_ecam_init()
169 LOG_DBG("Config space [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
170 data->cfg_phys_addr, (data->cfg_phys_addr + data->cfg_size - 1), data->cfg_size); in pcie_ecam_init()
171 LOG_DBG("Config mapped [0x%lx - 0x%lx, size 0x%lx]", in pcie_ecam_init()
172 data->cfg_addr, (data->cfg_addr + data->cfg_size - 1), data->cfg_size); in pcie_ecam_init()
181 struct pcie_ecam_data *data = dev->data; in pcie_ecam_ctrl_conf_read()
183 return pcie_generic_ctrl_conf_read(data->cfg_addr, bdf, reg); in pcie_ecam_ctrl_conf_read()
189 struct pcie_ecam_data *data = dev->data; in pcie_ecam_ctrl_conf_write()
191 pcie_generic_ctrl_conf_write(data->cfg_addr, bdf, reg, reg_data); in pcie_ecam_ctrl_conf_write()
200 addr = (((data->regions[type].bus_start + data->regions[type].allocation_offset) - 1) | in pcie_ecam_region_allocate_type()
201 ((bar_size) - 1)) + 1; in pcie_ecam_region_allocate_type()
203 if (addr - data->regions[type].bus_start + bar_size > data->regions[type].size) { in pcie_ecam_region_allocate_type()
208 data->regions[type].allocation_offset = addr - data->regions[type].bus_start + bar_size; in pcie_ecam_region_allocate_type()
217 struct pcie_ecam_data *data = dev->data; in pcie_ecam_region_allocate()
220 if (mem && !data->regions[PCIE_REGION_MEM64].size && in pcie_ecam_region_allocate()
221 !data->regions[PCIE_REGION_MEM].size) { in pcie_ecam_region_allocate()
226 if (!mem && !data->regions[PCIE_REGION_IO].size) { in pcie_ecam_region_allocate()
235 * - handle allocation from/to mem/mem64 when a region is full in pcie_ecam_region_allocate()
237 if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) || in pcie_ecam_region_allocate()
238 (data->regions[PCIE_REGION_MEM64].size && in pcie_ecam_region_allocate()
239 !data->regions[PCIE_REGION_MEM].size))) { in pcie_ecam_region_allocate()
254 struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data; in pcie_ecam_region_get_allocate_base()
257 if (mem && !data->regions[PCIE_REGION_MEM64].size && in pcie_ecam_region_get_allocate_base()
258 !data->regions[PCIE_REGION_MEM].size) { in pcie_ecam_region_get_allocate_base()
263 if (!mem && !data->regions[PCIE_REGION_IO].size) { in pcie_ecam_region_get_allocate_base()
272 * - handle allocation from/to mem/mem64 when a region is full in pcie_ecam_region_get_allocate_base()
274 if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) || in pcie_ecam_region_get_allocate_base()
275 (data->regions[PCIE_REGION_MEM64].size && in pcie_ecam_region_get_allocate_base()
276 !data->regions[PCIE_REGION_MEM].size))) { in pcie_ecam_region_get_allocate_base()
284 *bar_base_addr = (((data->regions[type].bus_start + in pcie_ecam_region_get_allocate_base()
285 data->regions[type].allocation_offset) - 1) | ((align) - 1)) + 1; in pcie_ecam_region_get_allocate_base()
294 struct pcie_ecam_data *data = dev->data; in pcie_ecam_region_translate()
302 if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) || in pcie_ecam_region_translate()
303 (data->regions[PCIE_REGION_MEM64].size && in pcie_ecam_region_translate()
304 !data->regions[PCIE_REGION_MEM].size))) { in pcie_ecam_region_translate()
312 *bar_addr = data->regions[type].phys_start + (bar_bus_addr - data->regions[type].bus_start); in pcie_ecam_region_translate()
322 const struct pcie_ctrl_config *cfg = (const struct pcie_ctrl_config *)dev->config; in pcie_ecam_msi_device_setup()
335 * re-allocating a proper table in ITS for each BDF since we can't be in pcie_ecam_msi_device_setup()
337 * Simply bail-out if it's the case here. in pcie_ecam_msi_device_setup()
348 ret = its_setup_deviceid(cfg->msi_parent, device_id, n_vector); in pcie_ecam_msi_device_setup()
354 vectors[i].arch.irq = its_alloc_intid(cfg->msi_parent); in pcie_ecam_msi_device_setup()
355 vectors[i].arch.address = its_get_msi_addr(cfg->msi_parent); in pcie_ecam_msi_device_setup()
359 ret = its_map_intid(cfg->msi_parent, device_id, in pcie_ecam_msi_device_setup()