4  * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/kernel.h>
8 #include <zephyr/drivers/pcie/msi.h>
9 #include <zephyr/drivers/pcie/cap.h>
15 	uint32_t base;  in pcie_msi_base()  local
21 	base = pcie_get_cap(bdf, PCI_CAP_ID_MSI);  in pcie_msi_base()
28 			base = base_msix;  in pcie_msi_base()
36 	return base;  in pcie_msi_base()
41 #include <zephyr/kernel/mm.h>
71 				    uint32_t base)  in get_msix_table_size()  argument
75 	mcr = pcie_conf_read(bdf, base + PCIE_MSIX_MCR);  in get_msix_table_size()
81 				   uint32_t base,  in map_msix_table_entries()  argument
91 	table_offset = pcie_conf_read(bdf, base + PCIE_MSIX_TR);  in map_msix_table_entries()
129 			    uint32_t base)  in get_msi_mmc()  argument
133 	mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);  in get_msi_mmc()
145 	uint32_t base;  in pcie_msi_vectors_allocate()  local
148 	base = pcie_msi_base(bdf, &msi);  in pcie_msi_vectors_allocate()
154 			req_vectors = get_msix_table_size(bdf, base);  in pcie_msi_vectors_allocate()
155 			if (!map_msix_table_entries(bdf, base,  in pcie_msi_vectors_allocate()
163 		req_vectors = get_msi_mmc(bdf, base);  in pcie_msi_vectors_allocate()
183 	uint32_t base;  in pcie_msi_vector_connect()  local
185 	base = pcie_msi_base(bdf, NULL);  in pcie_msi_vector_connect()
186 	if (base == 0U) {  in pcie_msi_vector_connect()
200 			uint32_t base,  in enable_msix()  argument
210 		sys_write32(map, (mm_reg_t) &vectors[i].msix_vector->msg_addr);  in enable_msix()
211 		sys_write32(0, (mm_reg_t) &vectors[i].msix_vector->msg_up_addr);  in enable_msix()
212 		sys_write32(mdr, (mm_reg_t) &vectors[i].msix_vector->msg_data);  in enable_msix()
213 		sys_write32(0, (mm_reg_t) &vectors[i].msix_vector->vector_ctrl);  in enable_msix()
216 	mcr = pcie_conf_read(bdf, base + PCIE_MSIX_MCR);  in enable_msix()
218 	pcie_conf_write(bdf, base + PCIE_MSIX_MCR, mcr);  in enable_msix()
226 			uint32_t base)  in disable_msi()  argument
230 	mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);  in disable_msi()
232 	pcie_conf_write(bdf, base + PCIE_MSI_MCR, mcr);  in disable_msi()
238 		       uint32_t base,  in enable_msi()  argument
247 	pcie_conf_write(bdf, base + PCIE_MSI_MAP0, map);  in enable_msi()
250 	mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);  in enable_msi()
252 		pcie_conf_write(bdf, base + PCIE_MSI_MAP1_64, 0U);  in enable_msi()
253 		pcie_conf_write(bdf, base + PCIE_MSI_MDR_64, mdr);  in enable_msi()
255 		pcie_conf_write(bdf, base + PCIE_MSI_MDR_32, mdr);  in enable_msi()
266 	pcie_conf_write(bdf, base + PCIE_MSI_MCR, mcr);  in enable_msi()
274 	uint32_t base;  in pcie_msi_enable()  local
277 	base = pcie_msi_base(bdf, &msi);  in pcie_msi_enable()
278 	if (base == 0U) {  in pcie_msi_enable()
283 		disable_msi(bdf, base);  in pcie_msi_enable()
284 		enable_msix(bdf, vectors, n_vector, base, irq);  in pcie_msi_enable()
286 		enable_msi(bdf, vectors, n_vector, base, irq);  in pcie_msi_enable()