Lines Matching +full:mspi +full:- +full:endian
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/mspi.h>
122 struct mspi_dw_data *dev_data = dev->data; in tx_data()
123 const struct mspi_dw_config *dev_config = dev->config; in tx_data()
124 const uint8_t *buf_pos = dev_data->buf_pos; in tx_data()
125 const uint8_t *buf_end = dev_data->buf_end; in tx_data()
135 uint8_t bytes_per_frame_exp = dev_data->bytes_per_frame_exp; in tx_data()
136 uint8_t tx_fifo_depth = dev_config->tx_fifo_depth_minus_1 + 1; in tx_data()
157 if (--room == 0) { in tx_data()
159 - FIELD_GET(TXFLR_TXTFL_MASK, read_txflr(dev)); in tx_data()
163 dev_data->buf_pos = (uint8_t *)buf_pos; in tx_data()
168 struct mspi_dw_data *dev_data = dev->data; in make_rx_cycles()
169 const struct mspi_dw_config *dev_config = dev->config; in make_rx_cycles()
170 uint16_t dummy_bytes = dev_data->dummy_bytes; in make_rx_cycles()
173 uint8_t tx_fifo_depth = dev_config->tx_fifo_depth_minus_1 + 1; in make_rx_cycles()
178 --dummy_bytes; in make_rx_cycles()
180 dev_data->dummy_bytes = 0; in make_rx_cycles()
184 if (--room == 0) { in make_rx_cycles()
186 - FIELD_GET(TXFLR_TXTFL_MASK, read_txflr(dev)); in make_rx_cycles()
190 dev_data->dummy_bytes = dummy_bytes; in make_rx_cycles()
197 struct mspi_dw_data *dev_data = dev->data; in read_rx_fifo()
198 const struct mspi_dw_config *dev_config = dev->config; in read_rx_fifo()
199 uint8_t bytes_to_discard = dev_data->bytes_to_discard; in read_rx_fifo()
200 uint8_t *buf_pos = dev_data->buf_pos; in read_rx_fifo()
201 const uint8_t *buf_end = &packet->data_buf[packet->num_bytes]; in read_rx_fifo()
202 uint8_t bytes_per_frame_exp = dev_data->bytes_per_frame_exp; in read_rx_fifo()
211 --bytes_to_discard; in read_rx_fifo()
225 dev_data->bytes_to_discard = bytes_to_discard; in read_rx_fifo()
226 dev_data->buf_pos = buf_pos; in read_rx_fifo()
231 if (--in_fifo == 0) { in read_rx_fifo()
236 remaining_frames = (bytes_to_discard + buf_end - buf_pos) in read_rx_fifo()
238 if (remaining_frames - 1 < dev_config->rx_fifo_threshold) { in read_rx_fifo()
239 write_rxftlr(dev, remaining_frames - 1); in read_rx_fifo()
242 dev_data->bytes_to_discard = bytes_to_discard; in read_rx_fifo()
243 dev_data->buf_pos = buf_pos; in read_rx_fifo()
248 struct mspi_dw_data *dev_data = dev->data; in mspi_dw_isr()
250 &dev_data->xfer.packets[dev_data->packets_done]; in mspi_dw_isr()
257 if (dev_data->buf_pos >= dev_data->buf_end) { in mspi_dw_isr()
266 k_sem_give(&dev_data->finished); in mspi_dw_isr()
269 if (dev_data->dummy_bytes) { in mspi_dw_isr()
286 return -ENOTSUP; in api_config()
292 dev_data->ctrlr0 &= ~CTRLR0_SPI_FRF_MASK; in apply_io_mode()
293 dev_data->spi_ctrlr0 &= ~SPI_CTRLR0_TRANS_TYPE_MASK; in apply_io_mode()
298 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SPI_FRF_MASK, in apply_io_mode()
300 dev_data->standard_spi = true; in apply_io_mode()
304 dev_data->standard_spi = false; in apply_io_mode()
310 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SPI_FRF_MASK, in apply_io_mode()
316 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SPI_FRF_MASK, in apply_io_mode()
322 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SPI_FRF_MASK, in apply_io_mode()
336 /* - both sent in Standard SPI mode */ in apply_io_mode()
337 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_TRANS_TYPE_MASK, in apply_io_mode()
343 /* - Instruction sent in Standard SPI mode, in apply_io_mode()
346 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_TRANS_TYPE_MASK, in apply_io_mode()
350 /* - both sent the same way as data. */ in apply_io_mode()
351 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_TRANS_TYPE_MASK, in apply_io_mode()
363 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_INST_L_MASK, in apply_cmd_length()
367 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_INST_L_MASK, in apply_cmd_length()
371 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_INST_L_MASK, in apply_cmd_length()
385 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_ADDR_L_MASK, in apply_addr_length()
395 enum mspi_io_mode io_mode = dev_data->xip_params_active.io_mode; in apply_xip_io_mode()
408 ctrl->read |= FIELD_PREP(XIP_CTRL_FRF_MASK, in apply_xip_io_mode()
410 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_FRF_MASK, in apply_xip_io_mode()
416 ctrl->read |= FIELD_PREP(XIP_CTRL_FRF_MASK, in apply_xip_io_mode()
418 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_FRF_MASK, in apply_xip_io_mode()
424 ctrl->read |= FIELD_PREP(XIP_CTRL_FRF_MASK, in apply_xip_io_mode()
426 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_FRF_MASK, in apply_xip_io_mode()
440 /* - both sent in Standard SPI mode */ in apply_xip_io_mode()
441 ctrl->read |= FIELD_PREP(XIP_CTRL_TRANS_TYPE_MASK, in apply_xip_io_mode()
443 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_TRANS_TYPE_MASK, in apply_xip_io_mode()
449 /* - Instruction sent in Standard SPI mode, in apply_xip_io_mode()
452 ctrl->read |= FIELD_PREP(XIP_CTRL_TRANS_TYPE_MASK, in apply_xip_io_mode()
454 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_TRANS_TYPE_MASK, in apply_xip_io_mode()
458 /* - both sent the same way as data. */ in apply_xip_io_mode()
459 ctrl->read |= FIELD_PREP(XIP_CTRL_TRANS_TYPE_MASK, in apply_xip_io_mode()
461 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_TRANS_TYPE_MASK, in apply_xip_io_mode()
472 uint8_t cmd_length = dev_data->xip_params_active.cmd_length; in apply_xip_cmd_length()
476 ctrl->read |= FIELD_PREP(XIP_CTRL_INST_L_MASK, in apply_xip_cmd_length()
478 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_INST_L_MASK, in apply_xip_cmd_length()
482 ctrl->read |= XIP_CTRL_INST_EN_BIT in apply_xip_cmd_length()
485 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_INST_L_MASK, in apply_xip_cmd_length()
489 ctrl->read |= XIP_CTRL_INST_EN_BIT in apply_xip_cmd_length()
492 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_INST_L_MASK, in apply_xip_cmd_length()
506 uint8_t addr_length = dev_data->xip_params_active.addr_length; in apply_xip_addr_length()
508 ctrl->read |= FIELD_PREP(XIP_CTRL_ADDR_L_MASK, addr_length * 2); in apply_xip_addr_length()
509 ctrl->write |= FIELD_PREP(XIP_WRITE_CTRL_ADDR_L_MASK, addr_length * 2); in apply_xip_addr_length()
519 const struct mspi_dw_config *dev_config = dev->config; in _api_dev_config()
520 struct mspi_dw_data *dev_data = dev->data; in _api_dev_config()
523 if (cfg->endian != MSPI_XFER_BIG_ENDIAN) { in _api_dev_config()
524 LOG_ERR("Only big endian transfers are supported."); in _api_dev_config()
525 return -ENOTSUP; in _api_dev_config()
530 if (cfg->ce_polarity != MSPI_CE_ACTIVE_LOW) { in _api_dev_config()
532 return -ENOTSUP; in _api_dev_config()
537 if (cfg->mem_boundary) { in _api_dev_config()
539 return -ENOTSUP; in _api_dev_config()
544 if (cfg->time_to_break) { in _api_dev_config()
546 return -ENOTSUP; in _api_dev_config()
552 dev_data->xip_params_stored.io_mode = cfg->io_mode; in _api_dev_config()
555 if (!apply_io_mode(dev_data, cfg->io_mode)) { in _api_dev_config()
556 return -EINVAL; in _api_dev_config()
565 if (!dev_data->xip_enabled) { in _api_dev_config()
566 dev_data->xip_cpp = cfg->cpp; in _api_dev_config()
567 } else if (dev_data->xip_cpp != cfg->cpp) { in _api_dev_config()
569 return -EINVAL; in _api_dev_config()
573 dev_data->ctrlr0 &= ~(CTRLR0_SCPOL_BIT | CTRLR0_SCPH_BIT); in _api_dev_config()
575 switch (cfg->cpp) { in _api_dev_config()
578 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SCPOL_BIT, 0) | in _api_dev_config()
582 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SCPOL_BIT, 0) | in _api_dev_config()
586 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SCPOL_BIT, 1) | in _api_dev_config()
590 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_SCPOL_BIT, 1) | in _api_dev_config()
597 if (cfg->freq > dev_config->clock_frequency / 2 || in _api_dev_config()
598 cfg->freq < dev_config->clock_frequency / 65534) { in _api_dev_config()
600 cfg->freq, dev_config->clock_frequency / 65534, in _api_dev_config()
601 dev_config->clock_frequency / 2); in _api_dev_config()
602 return -EINVAL; in _api_dev_config()
609 if (!dev_data->xip_enabled) { in _api_dev_config()
610 dev_data->xip_freq = cfg->freq; in _api_dev_config()
611 } else if (dev_data->xip_freq != cfg->freq) { in _api_dev_config()
613 return -EINVAL; in _api_dev_config()
617 dev_data->baudr = dev_config->clock_frequency / cfg->freq; in _api_dev_config()
622 if (cfg->data_rate != MSPI_DATA_RATE_SINGLE) { in _api_dev_config()
624 return -ENOTSUP; in _api_dev_config()
630 if (cfg->dqs_enable) { in _api_dev_config()
632 return -ENOTSUP; in _api_dev_config()
638 dev_data->xip_params_stored.read_cmd = cfg->read_cmd; in _api_dev_config()
641 dev_data->xip_params_stored.write_cmd = cfg->write_cmd; in _api_dev_config()
644 dev_data->xip_params_stored.rx_dummy = cfg->rx_dummy; in _api_dev_config()
647 dev_data->xip_params_stored.tx_dummy = cfg->tx_dummy; in _api_dev_config()
650 dev_data->xip_params_stored.cmd_length = cfg->cmd_length; in _api_dev_config()
653 dev_data->xip_params_stored.addr_length = cfg->addr_length; in _api_dev_config()
658 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_FRF_MASK, CTRLR0_FRF_SPI); in _api_dev_config()
660 dev_data->spi_ctrlr0 |= SPI_CTRLR0_CLK_STRETCH_EN_BIT; in _api_dev_config()
670 const struct mspi_dw_config *dev_config = dev->config; in api_dev_config()
671 struct mspi_dw_data *dev_data = dev->data; in api_dev_config()
674 if (dev_id != dev_data->dev_id) { in api_dev_config()
675 rc = k_sem_take(&dev_data->cfg_lock, in api_dev_config()
679 return -EBUSY; in api_dev_config()
682 dev_data->dev_id = dev_id; in api_dev_config()
686 !dev_config->sw_multi_periph) { in api_dev_config()
690 (void)k_sem_take(&dev_data->ctx_lock, K_FOREVER); in api_dev_config()
694 k_sem_give(&dev_data->ctx_lock); in api_dev_config()
697 dev_data->dev_id = NULL; in api_dev_config()
698 k_sem_give(&dev_data->cfg_lock); in api_dev_config()
708 struct mspi_dw_data *dev_data = dev->data; in api_get_channel_status()
710 (void)k_sem_take(&dev_data->ctx_lock, K_FOREVER); in api_get_channel_status()
712 dev_data->dev_id = NULL; in api_get_channel_status()
713 k_sem_give(&dev_data->cfg_lock); in api_get_channel_status()
715 k_sem_give(&dev_data->ctx_lock); in api_get_channel_status()
726 shift -= 8; in tx_control_field()
733 const struct mspi_dw_config *dev_config = dev->config; in start_next_packet()
734 struct mspi_dw_data *dev_data = dev->data; in start_next_packet()
736 &dev_data->xfer.packets[dev_data->packets_done]; in start_next_packet()
738 (dev_data->xip_enabled != 0), in start_next_packet()
746 if (packet->num_bytes == 0 && in start_next_packet()
747 dev_data->xfer.cmd_length == 0 && in start_next_packet()
748 dev_data->xfer.addr_length == 0) { in start_next_packet()
752 dev_data->dummy_bytes = 0; in start_next_packet()
754 dev_data->ctrlr0 &= ~CTRLR0_TMOD_MASK in start_next_packet()
757 dev_data->spi_ctrlr0 &= ~SPI_CTRLR0_WAIT_CYCLES_MASK; in start_next_packet()
759 if (dev_data->standard_spi && in start_next_packet()
760 (dev_data->xfer.cmd_length != 0 || in start_next_packet()
761 dev_data->xfer.addr_length != 0)) { in start_next_packet()
762 dev_data->bytes_per_frame_exp = 0; in start_next_packet()
763 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 7); in start_next_packet()
765 if ((packet->num_bytes % 4) == 0) { in start_next_packet()
766 dev_data->bytes_per_frame_exp = 2; in start_next_packet()
767 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 31); in start_next_packet()
768 } else if ((packet->num_bytes % 2) == 0) { in start_next_packet()
769 dev_data->bytes_per_frame_exp = 1; in start_next_packet()
770 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 15); in start_next_packet()
772 dev_data->bytes_per_frame_exp = 0; in start_next_packet()
773 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 7); in start_next_packet()
777 packet_frames = packet->num_bytes >> dev_data->bytes_per_frame_exp; in start_next_packet()
781 packet->num_bytes); in start_next_packet()
782 return -EINVAL; in start_next_packet()
785 if (packet->dir == MSPI_TX || packet->num_bytes == 0) { in start_next_packet()
787 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_TMOD_MASK, in start_next_packet()
789 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_WAIT_CYCLES_MASK, in start_next_packet()
790 dev_data->xfer.tx_dummy); in start_next_packet()
793 tx_fifo_threshold = dev_config->tx_fifo_threshold; in start_next_packet()
806 if (dev_data->standard_spi && in start_next_packet()
807 (dev_data->xfer.cmd_length != 0 || in start_next_packet()
808 dev_data->xfer.addr_length != 0)) { in start_next_packet()
811 dev_data->bytes_to_discard = dev_data->xfer.cmd_length in start_next_packet()
812 + dev_data->xfer.addr_length; in start_next_packet()
813 rx_total_bytes = dev_data->bytes_to_discard in start_next_packet()
814 + packet->num_bytes; in start_next_packet()
816 dev_data->dummy_bytes = packet->num_bytes; in start_next_packet()
820 tx_fifo_threshold = dev_config->tx_fifo_threshold; in start_next_packet()
821 /* For standard SPI, only 1-byte frames are used. */ in start_next_packet()
822 rx_fifo_threshold = MIN(rx_total_bytes - 1, in start_next_packet()
823 dev_config->rx_fifo_threshold); in start_next_packet()
828 rx_fifo_threshold = MIN(packet_frames - 1, in start_next_packet()
829 dev_config->rx_fifo_threshold); in start_next_packet()
832 dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_TMOD_MASK, tmod); in start_next_packet()
833 dev_data->spi_ctrlr0 |= FIELD_PREP(SPI_CTRLR0_WAIT_CYCLES_MASK, in start_next_packet()
834 dev_data->xfer.rx_dummy); in start_next_packet()
840 if (dev_data->dev_id->ce.port) { in start_next_packet()
841 rc = gpio_pin_set_dt(&dev_data->dev_id->ce, 1); in start_next_packet()
857 write_ctrlr0(dev, dev_data->ctrlr0); in start_next_packet()
859 ? FIELD_PREP(CTRLR1_NDF_MASK, packet_frames - 1) in start_next_packet()
861 write_spi_ctrlr0(dev, dev_data->spi_ctrlr0); in start_next_packet()
862 write_baudr(dev, dev_data->baudr); in start_next_packet()
863 write_ser(dev, BIT(dev_data->dev_id->dev_idx)); in start_next_packet()
870 dev_data->buf_pos = packet->data_buf; in start_next_packet()
871 dev_data->buf_end = &packet->data_buf[packet->num_bytes]; in start_next_packet()
873 if ((imr & IMR_TXEIM_BIT) && dev_data->buf_pos < dev_data->buf_end) { in start_next_packet()
876 if (dev_data->dummy_bytes) { in start_next_packet()
877 uint32_t tx_total = dev_data->bytes_to_discard in start_next_packet()
878 + dev_data->dummy_bytes; in start_next_packet()
880 if (start_level > tx_total - 1) { in start_next_packet()
881 start_level = tx_total - 1; in start_next_packet()
897 if (dev_data->standard_spi) { in start_next_packet()
898 if (dev_data->xfer.cmd_length) { in start_next_packet()
899 tx_control_field(dev, packet->cmd, in start_next_packet()
900 dev_data->xfer.cmd_length); in start_next_packet()
903 if (dev_data->xfer.addr_length) { in start_next_packet()
904 tx_control_field(dev, packet->address, in start_next_packet()
905 dev_data->xfer.addr_length); in start_next_packet()
908 if (dev_data->xfer.cmd_length) { in start_next_packet()
909 write_dr(dev, packet->cmd); in start_next_packet()
912 if (dev_data->xfer.addr_length) { in start_next_packet()
913 write_dr(dev, packet->address); in start_next_packet()
917 if (dev_data->dummy_bytes) { in start_next_packet()
921 } else if (packet->dir == MSPI_TX && packet->num_bytes) { in start_next_packet()
928 rc = k_sem_take(&dev_data->finished, timeout); in start_next_packet()
930 rc = -ETIMEDOUT; in start_next_packet()
941 if (rc == -ETIMEDOUT) { in start_next_packet()
953 if (dev_data->dev_id->ce.port) { in start_next_packet()
957 rc2 = gpio_pin_set_dt(&dev_data->dev_id->ce, 0); in start_next_packet()
970 struct mspi_dw_data *dev_data = dev->data; in _api_transceive()
973 dev_data->spi_ctrlr0 &= ~SPI_CTRLR0_WAIT_CYCLES_MASK in _api_transceive()
977 if (!apply_cmd_length(dev_data, req->cmd_length) || in _api_transceive()
978 !apply_addr_length(dev_data, req->addr_length)) { in _api_transceive()
979 return -EINVAL; in _api_transceive()
982 if (dev_data->standard_spi && in _api_transceive()
983 (req->rx_dummy != 0 || req->tx_dummy != 0)) { in _api_transceive()
985 return -EINVAL; in _api_transceive()
986 } else if (req->rx_dummy > SPI_CTRLR0_WAIT_CYCLES_MAX || in _api_transceive()
987 req->tx_dummy > SPI_CTRLR0_WAIT_CYCLES_MAX) { in _api_transceive()
989 req->rx_dummy, req->tx_dummy); in _api_transceive()
990 return -EINVAL; in _api_transceive()
993 dev_data->xfer = *req; in _api_transceive()
995 for (dev_data->packets_done = 0; in _api_transceive()
996 dev_data->packets_done < dev_data->xfer.num_packet; in _api_transceive()
997 dev_data->packets_done++) { in _api_transceive()
998 rc = start_next_packet(dev, K_MSEC(dev_data->xfer.timeout)); in _api_transceive()
1011 struct mspi_dw_data *dev_data = dev->data; in api_transceive()
1014 if (dev_id != dev_data->dev_id) { in api_transceive()
1016 return -EINVAL; in api_transceive()
1020 if (req->async) { in api_transceive()
1022 return -ENOTSUP; in api_transceive()
1031 (void)k_sem_take(&dev_data->ctx_lock, K_FOREVER); in api_transceive()
1033 if (dev_data->suspended) { in api_transceive()
1034 rc = -EFAULT; in api_transceive()
1039 k_sem_give(&dev_data->ctx_lock); in api_transceive()
1055 struct mspi_dw_data *dev_data = dev->data; in _api_xip_config()
1058 if (!cfg->enable) { in _api_xip_config()
1064 dev_data->xip_enabled &= ~BIT(dev_id->dev_idx); in _api_xip_config()
1066 if (!dev_data->xip_enabled) { in _api_xip_config()
1082 if (!dev_data->xip_enabled) { in _api_xip_config()
1083 struct xip_params *params = &dev_data->xip_params_active; in _api_xip_config()
1086 *params = dev_data->xip_params_stored; in _api_xip_config()
1091 return -EINVAL; in _api_xip_config()
1094 if (params->rx_dummy > SPI_CTRLR0_WAIT_CYCLES_MAX || in _api_xip_config()
1095 params->tx_dummy > SPI_CTRLR0_WAIT_CYCLES_MAX) { in _api_xip_config()
1097 params->rx_dummy, params->tx_dummy); in _api_xip_config()
1098 return -EINVAL; in _api_xip_config()
1111 params->rx_dummy); in _api_xip_config()
1113 params->tx_dummy); in _api_xip_config()
1117 * non-XIP transfers have not been performed yet. in _api_xip_config()
1119 write_ctrlr0(dev, dev_data->ctrlr0); in _api_xip_config()
1120 write_baudr(dev, dev_data->baudr); in _api_xip_config()
1122 write_xip_incr_inst(dev, params->read_cmd); in _api_xip_config()
1123 write_xip_wrap_inst(dev, params->read_cmd); in _api_xip_config()
1125 write_xip_write_incr_inst(dev, params->write_cmd); in _api_xip_config()
1126 write_xip_write_wrap_inst(dev, params->write_cmd); in _api_xip_config()
1128 } else if (dev_data->xip_params_active.read_cmd != in _api_xip_config()
1129 dev_data->xip_params_stored.read_cmd || in _api_xip_config()
1130 dev_data->xip_params_active.write_cmd != in _api_xip_config()
1131 dev_data->xip_params_stored.write_cmd || in _api_xip_config()
1132 dev_data->xip_params_active.cmd_length != in _api_xip_config()
1133 dev_data->xip_params_stored.cmd_length || in _api_xip_config()
1134 dev_data->xip_params_active.addr_length != in _api_xip_config()
1135 dev_data->xip_params_stored.addr_length || in _api_xip_config()
1136 dev_data->xip_params_active.rx_dummy != in _api_xip_config()
1137 dev_data->xip_params_stored.rx_dummy || in _api_xip_config()
1138 dev_data->xip_params_active.tx_dummy != in _api_xip_config()
1139 dev_data->xip_params_stored.tx_dummy) { in _api_xip_config()
1141 return -EINVAL; in _api_xip_config()
1151 dev_data->xip_enabled |= BIT(dev_id->dev_idx); in _api_xip_config()
1160 struct mspi_dw_data *dev_data = dev->data; in api_xip_config()
1163 if (cfg->enable && dev_id != dev_data->dev_id) { in api_xip_config()
1165 return -EINVAL; in api_xip_config()
1174 (void)k_sem_take(&dev_data->ctx_lock, K_FOREVER); in api_xip_config()
1176 if (dev_data->suspended) { in api_xip_config()
1177 rc = -EFAULT; in api_xip_config()
1182 k_sem_give(&dev_data->ctx_lock); in api_xip_config()
1197 struct mspi_dw_data *dev_data = dev->data; in dev_pm_action_cb()
1201 const struct mspi_dw_config *dev_config = dev->config; in dev_pm_action_cb()
1202 int rc = pinctrl_apply_state(dev_config->pcfg, in dev_pm_action_cb()
1212 dev_data->suspended = false; in dev_pm_action_cb()
1220 (dev_data->xip_enabled != 0), in dev_pm_action_cb()
1224 const struct mspi_dw_config *dev_config = dev->config; in dev_pm_action_cb()
1225 int rc = pinctrl_apply_state(dev_config->pcfg, in dev_pm_action_cb()
1234 k_sem_take(&dev_data->ctx_lock, K_NO_WAIT) != 0) { in dev_pm_action_cb()
1236 return -EBUSY; in dev_pm_action_cb()
1239 dev_data->suspended = true; in dev_pm_action_cb()
1243 k_sem_give(&dev_data->ctx_lock); in dev_pm_action_cb()
1248 return -ENOTSUP; in dev_pm_action_cb()
1253 struct mspi_dw_data *dev_data = dev->data; in dev_init()
1254 const struct mspi_dw_config *dev_config = dev->config; in dev_init()
1262 dev_config->irq_config(); in dev_init()
1264 k_sem_init(&dev_data->finished, 0, 1); in dev_init()
1265 k_sem_init(&dev_data->cfg_lock, 1, 1); in dev_init()
1266 k_sem_init(&dev_data->ctx_lock, 1, 1); in dev_init()
1268 for (ce_gpio = dev_config->ce_gpios; in dev_init()
1269 ce_gpio < &dev_config->ce_gpios[dev_config->ce_gpios_len]; in dev_init()
1271 if (!device_is_ready(ce_gpio->port)) { in dev_init()
1273 ce_gpio->port->name); in dev_init()
1274 return -ENODEV; in dev_init()
1285 rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP); in dev_init()
1296 static DEVICE_API(mspi, drv_api) = {
1338 .tx_fifo_depth_minus_1 = TX_FIFO_DEPTH(inst) - 1, \
1341 7 * TX_FIFO_DEPTH(inst) / 8 - 1), \
1344 1 * RX_FIFO_DEPTH(inst) / 8 - 1)