35 	struct mspi_xfer              xfer;  member
189 		if (ctx->xfer.hold_ce &&  in mspi_context_ce_control()
190 		    ctx->xfer.ce_sw_ctrl.gpio.port != NULL) {  in mspi_context_ce_control()
192 				gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 1);  in mspi_context_ce_control()
193 				k_busy_wait(ctx->xfer.ce_sw_ctrl.delay);  in mspi_context_ce_control()
195 				k_busy_wait(ctx->xfer.ce_sw_ctrl.delay);  in mspi_context_ce_control()
196 				gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 0);  in mspi_context_ce_control()
220 				    const struct mspi_xfer *xfer,  in mspi_context_lock()  argument
232 	if (k_sem_take(&ctx->lock, K_MSEC(xfer->timeout))) {  in mspi_context_lock()
235 	if (ctx->xfer.async) {  in mspi_context_lock()
236 		if ((xfer->tx_dummy == ctx->xfer.tx_dummy) &&  in mspi_context_lock()
237 		    (xfer->rx_dummy == ctx->xfer.rx_dummy) &&  in mspi_context_lock()
238 		    (xfer->cmd_length == ctx->xfer.cmd_length) &&  in mspi_context_lock()
239 		    (xfer->addr_length == ctx->xfer.addr_length)) {  in mspi_context_lock()
257 	ctx->xfer            = *xfer;  in mspi_context_lock()
259 	ctx->packets_left    = ctx->xfer.num_packet;  in mspi_context_lock()
359 			    const struct mspi_xfer *xfer)  in mspi_xfer_config()  argument
387 	if (xfer->cmd_length > AM_HAL_MSPI_INSTR_2_BYTE + 1) {  in mspi_xfer_config()
391 	if (xfer->cmd_length == 0) {  in mspi_xfer_config()
395 		hal_dev_cfg.eInstrCfg  = xfer->cmd_length - 1;  in mspi_xfer_config()
398 	if (xfer->addr_length > AM_HAL_MSPI_ADDR_4_BYTE + 1) {  in mspi_xfer_config()
402 	if (xfer->addr_length == 0) {  in mspi_xfer_config()
406 		hal_dev_cfg.eAddrCfg  = xfer->addr_length - 1;  in mspi_xfer_config()
409 	hal_dev_cfg.bTurnaround     = (xfer->rx_dummy != 0);  in mspi_xfer_config()
410 	hal_dev_cfg.ui8TurnAround   = (uint8_t)xfer->rx_dummy;  in mspi_xfer_config()
411 	hal_dev_cfg.bEnWriteLatency = (xfer->tx_dummy != 0);  in mspi_xfer_config()
412 	hal_dev_cfg.ui8WriteLatency = (uint8_t)xfer->tx_dummy;  in mspi_xfer_config()
962 	const struct mspi_xfer *xfer = &data->ctx.xfer;  in mspi_pio_prepare()  local
966 	trans->bSendAddr      = (xfer->addr_length != 0);  in mspi_pio_prepare()
967 	trans->bSendInstr     = (xfer->cmd_length != 0);  in mspi_pio_prepare()
968 	trans->bTurnaround    = (xfer->rx_dummy != 0);  in mspi_pio_prepare()
969 	trans->bEnWRLatency   = (xfer->tx_dummy != 0);  in mspi_pio_prepare()
974 	if (xfer->cmd_length > AM_HAL_MSPI_INSTR_2_BYTE + 1) {  in mspi_pio_prepare()
978 	if (xfer->cmd_length != 0) {  in mspi_pio_prepare()
979 		am_hal_mspi_instr_e eInstrCfg = xfer->cmd_length - 1;  in mspi_pio_prepare()
989 	data->dev_cfg.cmd_length = xfer->cmd_length;  in mspi_pio_prepare()
991 	if (xfer->addr_length > AM_HAL_MSPI_ADDR_4_BYTE + 1) {  in mspi_pio_prepare()
995 	if (xfer->addr_length != 0) {  in mspi_pio_prepare()
996 		am_hal_mspi_addr_e eAddrCfg = xfer->addr_length - 1;  in mspi_pio_prepare()
1005 	data->dev_cfg.addr_length = xfer->addr_length;  in mspi_pio_prepare()
1011 			       const struct mspi_xfer *xfer,  in mspi_pio_transceive()  argument
1024 	if (xfer->num_packet == 0 ||  in mspi_pio_transceive()
1025 	    !xfer->packets ||  in mspi_pio_transceive()
1026 	    xfer->timeout > CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE) {  in mspi_pio_transceive()
1030 	cfg_flag = mspi_context_lock(ctx, data->dev_id, xfer, cb, cb_ctx, true);  in mspi_pio_transceive()
1046 	if (!ctx->xfer.async) {  in mspi_pio_transceive()
1049 			packet_idx               = ctx->xfer.num_packet - ctx->packets_left;  in mspi_pio_transceive()
1050 			packet                   = &ctx->xfer.packets[packet_idx];  in mspi_pio_transceive()
1076 			packet_idx               = ctx->xfer.num_packet - ctx->packets_left;  in mspi_pio_transceive()
1077 			packet                   = &ctx->xfer.packets[packet_idx];  in mspi_pio_transceive()
1119 			       const struct mspi_xfer *xfer,  in mspi_dma_transceive()  argument
1130 	if (xfer->num_packet == 0 ||  in mspi_dma_transceive()
1131 	    !xfer->packets ||  in mspi_dma_transceive()
1132 	    xfer->timeout > CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE) {  in mspi_dma_transceive()
1136 	cfg_flag = mspi_context_lock(ctx, data->dev_id, xfer, cb, cb_ctx, true);  in mspi_dma_transceive()
1142 			ret = mspi_xfer_config(controller, xfer);  in mspi_dma_transceive()
1160 		uint32_t packet_idx = ctx->xfer.num_packet - ctx->packets_left;  in mspi_dma_transceive()
1163 		packet                     = &ctx->xfer.packets[packet_idx];  in mspi_dma_transceive()
1164 		trans.ui8Priority          = ctx->xfer.priority;  in mspi_dma_transceive()
1172 		if (ctx->xfer.async) {  in mspi_dma_transceive()
1207 	if (!ctx->xfer.async) {  in mspi_dma_transceive()
1208 		while (ctx->packets_done < ctx->xfer.num_packet) {  in mspi_dma_transceive()
1220 				 const struct mspi_xfer *xfer)  in mspi_ambiq_transceive()  argument
1232 	if (xfer->async) {  in mspi_ambiq_transceive()
1237 	if (xfer->xfer_mode == MSPI_PIO) {  in mspi_ambiq_transceive()
1238 		return mspi_pio_transceive(controller, xfer, cb, cb_ctx);  in mspi_ambiq_transceive()
1239 	} else if (xfer->xfer_mode == MSPI_DMA) {  in mspi_ambiq_transceive()
1240 		return mspi_dma_transceive(controller, xfer, cb, cb_ctx);  in mspi_ambiq_transceive()