4  * SPDX-License-Identifier: Apache-2.0
55 		/* Dummy SCLK cycles between TX and RX (for SPI mode) */
58 		/* Use auto repeat mode */
60 		/* Tearing enable sync mode */
62 		/* TRX command timeout mode */
90 struct stream {  struct
119 	struct stream dma_stream;
153 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_reset_state()
154 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_reset_state()
156 	base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK;  in mipi_dbi_lcdic_reset_state()
158 	base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK;  in mipi_dbi_lcdic_reset_state()
168 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_start_dma()
169 	struct mipi_dbi_lcdic_data *data = dev->data;  in mipi_dbi_lcdic_start_dma()
170 	struct stream *stream = &data->dma_stream;  in mipi_dbi_lcdic_start_dma()  local
171 	uint32_t aligned_len = data->cmd_bytes & (~0x3);  in mipi_dbi_lcdic_start_dma()
172 	uint32_t unaligned_len = data->cmd_bytes & 0x3;  in mipi_dbi_lcdic_start_dma()
175 	stream->dma_cfg.head_block = &stream->blk_cfg[0];  in mipi_dbi_lcdic_start_dma()
179 		stream->blk_cfg[0].source_address = (uint32_t)&data->unaligned_word;  in mipi_dbi_lcdic_start_dma()
180 		stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA;  in mipi_dbi_lcdic_start_dma()
182 		stream->blk_cfg[0].block_size = sizeof(uint32_t);  in mipi_dbi_lcdic_start_dma()
183 		stream->dma_cfg.block_count = 1;  in mipi_dbi_lcdic_start_dma()
184 		stream->blk_cfg[0].next_block = NULL;  in mipi_dbi_lcdic_start_dma()
187 		stream->blk_cfg[0].source_address = (uint32_t)data->xfer_buf;  in mipi_dbi_lcdic_start_dma()
188 		stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA;  in mipi_dbi_lcdic_start_dma()
190 		stream->blk_cfg[0].block_size = aligned_len;  in mipi_dbi_lcdic_start_dma()
193 			stream->dma_cfg.block_count = 2;  in mipi_dbi_lcdic_start_dma()
194 			stream->blk_cfg[0].next_block =  in mipi_dbi_lcdic_start_dma()
195 						&stream->blk_cfg[1];  in mipi_dbi_lcdic_start_dma()
196 			stream->blk_cfg[1].source_address =  in mipi_dbi_lcdic_start_dma()
197 				(uint32_t)&data->unaligned_word;  in mipi_dbi_lcdic_start_dma()
198 			stream->blk_cfg[1].dest_address =  in mipi_dbi_lcdic_start_dma()
199 				(uint32_t)&config->base->TFIFO_WDATA;  in mipi_dbi_lcdic_start_dma()
200 			stream->blk_cfg[1].block_size = sizeof(uint32_t);  in mipi_dbi_lcdic_start_dma()
202 			stream->dma_cfg.block_count = 1;  in mipi_dbi_lcdic_start_dma()
203 			stream->blk_cfg[0].next_block = NULL;  in mipi_dbi_lcdic_start_dma()
207 	ret = dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);  in mipi_dbi_lcdic_start_dma()
215 	ret = dma_start(stream->dma_dev, stream->channel);  in mipi_dbi_lcdic_start_dma()
220 	config->base->CTRL |= LCDIC_CTRL_DMA_EN_MASK;  in mipi_dbi_lcdic_start_dma()
239 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_configure()
240 	struct mipi_dbi_lcdic_data *data = dev->data;  in mipi_dbi_lcdic_configure()
241 	const struct spi_config *spi_cfg = &dbi_config->config;  in mipi_dbi_lcdic_configure()
242 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_configure()
246 	if (dbi_config == data->active_cfg) {  in mipi_dbi_lcdic_configure()
251 	base->ICR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_configure()
253 	base->IMR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_configure()
256 	ret = clock_control_set_rate(config->clock_dev, config->clock_subsys,  in mipi_dbi_lcdic_configure()
257 			(clock_control_subsys_rate_t)spi_cfg->frequency);  in mipi_dbi_lcdic_configure()
259 		LOG_ERR("Invalid clock frequency %d", spi_cfg->frequency);  in mipi_dbi_lcdic_configure()
262 	if (spi_cfg->slave != 0) {  in mipi_dbi_lcdic_configure()
264 		return -ENOTSUP;  in mipi_dbi_lcdic_configure()
266 	if (SPI_WORD_SIZE_GET(spi_cfg->operation) > 8) {  in mipi_dbi_lcdic_configure()
268 		return -ENOTSUP;  in mipi_dbi_lcdic_configure()
271 	reg = base->CTRL;  in mipi_dbi_lcdic_configure()
274 	if (dbi_config->mode == MIPI_DBI_MODE_8080_BUS_8_BIT) {  in mipi_dbi_lcdic_configure()
275 		/* Enable 8080 Mode */  in mipi_dbi_lcdic_configure()
277 	} else if (dbi_config->mode == MIPI_DBI_MODE_SPI_4WIRE) {  in mipi_dbi_lcdic_configure()
278 		/* Select SPI 4 wire mode */  in mipi_dbi_lcdic_configure()
281 	} else if (dbi_config->mode == MIPI_DBI_MODE_SPI_3WIRE) {  in mipi_dbi_lcdic_configure()
282 		/* Select SPI 3 wire mode */  in mipi_dbi_lcdic_configure()
286 		/* Unsupported mode */  in mipi_dbi_lcdic_configure()
287 		return -ENOTSUP;  in mipi_dbi_lcdic_configure()
289 	/* If using SPI mode, validate that half-duplex was requested */  in mipi_dbi_lcdic_configure()
291 	    (!(spi_cfg->operation & SPI_HALF_DUPLEX))) {  in mipi_dbi_lcdic_configure()
293 		return -ENOTSUP;  in mipi_dbi_lcdic_configure()
297 		LCDIC_CTRL_DAT_ENDIAN(!config->swap_bytes);  in mipi_dbi_lcdic_configure()
300 	base->CTRL = reg;  in mipi_dbi_lcdic_configure()
304 	reg = base->SPI_CTRL;  in mipi_dbi_lcdic_configure()
306 		LCDIC_SPI_CTRL_SDAT_ENDIAN((spi_cfg->operation &  in mipi_dbi_lcdic_configure()
309 		LCDIC_SPI_CTRL_CPHA((spi_cfg->operation & SPI_MODE_CPHA) ? 1 : 0);  in mipi_dbi_lcdic_configure()
311 		LCDIC_SPI_CTRL_CPOL((spi_cfg->operation & SPI_MODE_CPOL) ? 1 : 0);  in mipi_dbi_lcdic_configure()
312 	base->SPI_CTRL = reg;  in mipi_dbi_lcdic_configure()
318 	base->I8080_CTRL1 = LCDIC_I8080_CTRL1_TRIW(0xf) |  in mipi_dbi_lcdic_configure()
320 			LCDIC_I8080_CTRL1_TWIW(config->write_inactive_min) |  in mipi_dbi_lcdic_configure()
321 			LCDIC_I8080_CTRL1_TWAW(config->write_active_min);  in mipi_dbi_lcdic_configure()
324 	base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK;  in mipi_dbi_lcdic_configure()
327 	data->active_cfg = dbi_config;  in mipi_dbi_lcdic_configure()
340 	uint32_t aligned_len = buf_len - unaligned_len;  in mipi_dbi_lcdic_get_unaligned()
342 	while ((unaligned_len--)) {  in mipi_dbi_lcdic_get_unaligned()
364 			base->TFIFO_WDATA = last_word;  in mipi_dbi_lcdic_fill_tx()
368 			base->TFIFO_WDATA = word_buf[bytes_written >> 2];  in mipi_dbi_lcdic_fill_tx()
371 		if (base->IRSR & LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_MASK) {  in mipi_dbi_lcdic_fill_tx()
375 			base->ICR |= LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_MASK;  in mipi_dbi_lcdic_fill_tx()
379 		buf_len -= write_len;  in mipi_dbi_lcdic_fill_tx()
396 	cmd.bits.data_len = buf_len - 1;  in mipi_dbi_lcdic_set_cmd()
403 	base->TFIFO_WDATA = cmd.u32;  in mipi_dbi_lcdic_set_cmd()
412 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_write_display()
413 	struct mipi_dbi_lcdic_data *dev_data = dev->data;  in mipi_dbi_lcdic_write_display()
414 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_write_display()
419 	ret = k_sem_take(&dev_data->lock, K_FOREVER);  in mipi_dbi_lcdic_write_display()
429 	if (dev_data->new_frame) {  in mipi_dbi_lcdic_write_display()
430 		switch (dev_data->te_edge) {  in mipi_dbi_lcdic_write_display()
441 		dev_data->new_frame = false;  in mipi_dbi_lcdic_write_display()
444 	if (!desc->frame_incomplete) {  in mipi_dbi_lcdic_write_display()
446 		dev_data->new_frame = true;  in mipi_dbi_lcdic_write_display()
452 	if (desc->buf_size != 0) {  in mipi_dbi_lcdic_write_display()
453 		dev_data->xfer_bytes = desc->buf_size;  in mipi_dbi_lcdic_write_display()
455 		dev_data->cmd_bytes = MIN(desc->buf_size, LCDIC_MAX_XFER);  in mipi_dbi_lcdic_write_display()
456 		dev_data->xfer_buf = framebuf;  in mipi_dbi_lcdic_write_display()
461 		if (dev_data->cmd_bytes & 0x3) {  in mipi_dbi_lcdic_write_display()
462 			dev_data->unaligned_word = mipi_dbi_lcdic_get_unaligned(  in mipi_dbi_lcdic_write_display()
463 							dev_data->xfer_buf,  in mipi_dbi_lcdic_write_display()
464 							dev_data->cmd_bytes);  in mipi_dbi_lcdic_write_display()
469 			dev_data->pixel_fmt = LCDIC_DATA_FMT_WORD;  in mipi_dbi_lcdic_write_display()
471 			dev_data->pixel_fmt = LCDIC_DATA_FMT_HALFWORD;  in mipi_dbi_lcdic_write_display()
473 			dev_data->pixel_fmt = LCDIC_DATA_FMT_BYTE;  in mipi_dbi_lcdic_write_display()
475 			if (config->swap_bytes) {  in mipi_dbi_lcdic_write_display()
483 				       dev_data->pixel_fmt,  in mipi_dbi_lcdic_write_display()
485 				       dev_data->cmd_bytes);  in mipi_dbi_lcdic_write_display()
490 		base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_display()
506 		base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_display()
508 		ret = k_sem_take(&dev_data->xfer_sem, K_FOREVER);  in mipi_dbi_lcdic_write_display()
511 	k_sem_give(&dev_data->lock);  in mipi_dbi_lcdic_write_display()
522 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_write_cmd()
523 	struct mipi_dbi_lcdic_data *dev_data = dev->data;  in mipi_dbi_lcdic_write_cmd()
524 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_write_cmd()
528 	ret = k_sem_take(&dev_data->lock, K_FOREVER);  in mipi_dbi_lcdic_write_cmd()
545 	dev_data->pixel_fmt = LCDIC_DATA_FMT_BYTE;  in mipi_dbi_lcdic_write_cmd()
546 	base->TFIFO_WDATA = cmd;  in mipi_dbi_lcdic_write_cmd()
548 	while ((base->IRSR & LCDIC_IRSR_CMD_DONE_RAW_INTR_MASK) == 0) {  in mipi_dbi_lcdic_write_cmd()
551 	base->ICR |= LCDIC_ICR_CMD_DONE_INTR_CLR_MASK;  in mipi_dbi_lcdic_write_cmd()
554 		dev_data->xfer_bytes = data_len;  in mipi_dbi_lcdic_write_cmd()
556 		dev_data->cmd_bytes = MIN(data_len, LCDIC_MAX_XFER);  in mipi_dbi_lcdic_write_cmd()
557 		dev_data->xfer_buf = data;  in mipi_dbi_lcdic_write_cmd()
562 		if (dev_data->cmd_bytes & 0x3) {  in mipi_dbi_lcdic_write_cmd()
563 			dev_data->unaligned_word = mipi_dbi_lcdic_get_unaligned(  in mipi_dbi_lcdic_write_cmd()
564 							dev_data->xfer_buf,  in mipi_dbi_lcdic_write_cmd()
565 							dev_data->cmd_bytes);  in mipi_dbi_lcdic_write_cmd()
570 				       dev_data->cmd_bytes);  in mipi_dbi_lcdic_write_cmd()
572 		if (((((uint32_t)dev_data->xfer_buf) & 0x3) == 0) ||  in mipi_dbi_lcdic_write_cmd()
573 		    (dev_data->cmd_bytes < 4)) {  in mipi_dbi_lcdic_write_cmd()
578 			base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_cmd()
596 			base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_cmd()
598 		ret = k_sem_take(&dev_data->xfer_sem, K_FOREVER);  in mipi_dbi_lcdic_write_cmd()
601 	k_sem_give(&dev_data->lock);  in mipi_dbi_lcdic_write_cmd()
607 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_reset()
608 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_reset()
618 	if (clock_control_get_rate(config->clock_dev, config->clock_subsys,  in mipi_dbi_lcdic_reset()
620 		return -EIO;  in mipi_dbi_lcdic_reset()
622 	rst_width = (delay_ms * (lcdic_freq)) / ((1 << config->timer0_ratio) * MSEC_PER_SEC);  in mipi_dbi_lcdic_reset()
626 	pulse_cnt = ((rst_width + (LCDIC_MAX_RST_WIDTH - 1)) / LCDIC_MAX_RST_WIDTH);  in mipi_dbi_lcdic_reset()
629 	if ((pulse_cnt - 1) > LCDIC_MAX_RST_PULSE_COUNT) {  in mipi_dbi_lcdic_reset()
636 	base->RST_CTRL = LCDIC_RST_CTRL_RST_WIDTH(rst_width - 1) |  in mipi_dbi_lcdic_reset()
637 			LCDIC_RST_CTRL_RST_SEQ_NUM(pulse_cnt - 1) |  in mipi_dbi_lcdic_reset()
640 	while ((base->IRSR & LCDIC_IRSR_RST_DONE_RAW_INTR_MASK) == 0) {  in mipi_dbi_lcdic_reset()
643 	base->ICR |= LCDIC_ICR_RST_DONE_INTR_CLR_MASK;  in mipi_dbi_lcdic_reset()
651 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_configure_te()
652 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_configure_te()
653 	struct mipi_dbi_lcdic_data *data = dev->data;  in mipi_dbi_lcdic_configure_te()
663 	if (clock_control_get_rate(config->clock_dev, config->clock_subsys,  in mipi_dbi_lcdic_configure_te()
665 		return -EIO;  in mipi_dbi_lcdic_configure_te()
674 	ttew = lcdic_freq / (1 << config->timer0_ratio);  in mipi_dbi_lcdic_configure_te()
676 	ttew /= (1 << config->timer1_ratio);  in mipi_dbi_lcdic_configure_te()
682 		return -ENOTSUP;  in mipi_dbi_lcdic_configure_te()
684 	reg = base->TE_CTRL;  in mipi_dbi_lcdic_configure_te()
687 	base->TE_CTRL = reg;  in mipi_dbi_lcdic_configure_te()
688 	data->te_edge = edge;  in mipi_dbi_lcdic_configure_te()
696 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_init()
697 	struct mipi_dbi_lcdic_data *data = dev->data;  in mipi_dbi_lcdic_init()
698 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_init()
701 	ret = clock_control_on(config->clock_dev, config->clock_subsys);  in mipi_dbi_lcdic_init()
707 	ret = clock_control_set_rate(config->clock_dev, config->clock_subsys,  in mipi_dbi_lcdic_init()
713 	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);  in mipi_dbi_lcdic_init()
717 	ret = k_sem_init(&data->xfer_sem, 0, 1);  in mipi_dbi_lcdic_init()
721 	ret = k_sem_init(&data->lock, 1, 1);  in mipi_dbi_lcdic_init()
726 	base->ICR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_init()
728 	base->IMR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_init()
731 	config->irq_config_func(dev);  in mipi_dbi_lcdic_init()
734 	base->FIFO_CTRL = LCDIC_FIFO_CTRL_RFIFO_THRES(LCDIC_RX_FIFO_THRESH) |  in mipi_dbi_lcdic_init()
737 	base->TO_CTRL &= ~(LCDIC_TO_CTRL_CMD_LONG_TO_MASK |  in mipi_dbi_lcdic_init()
741 	base->TIMER_CTRL = LCDIC_TIMER_CTRL_TIMER_RATIO1(config->timer1_ratio) |  in mipi_dbi_lcdic_init()
742 			LCDIC_TIMER_CTRL_TIMER_RATIO0(config->timer0_ratio);  in mipi_dbi_lcdic_init()
744 	data->te_edge = MIPI_DBI_TE_NO_EDGE;  in mipi_dbi_lcdic_init()
750 	INPUTMUX_AttachSignal(INPUTMUX, data->dma_stream.channel,  in mipi_dbi_lcdic_init()
768 	const struct mipi_dbi_lcdic_config *config = dev->config;  in mipi_dbi_lcdic_isr()
769 	struct mipi_dbi_lcdic_data *data = dev->data;  in mipi_dbi_lcdic_isr()
770 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_isr()
773 	isr_status = base->ISR;  in mipi_dbi_lcdic_isr()
775 	base->ICR |= isr_status;  in mipi_dbi_lcdic_isr()
778 		if (config->base->CTRL & LCDIC_CTRL_DMA_EN_MASK) {  in mipi_dbi_lcdic_isr()
780 			data->xfer_bytes -= data->cmd_bytes;  in mipi_dbi_lcdic_isr()
781 			data->xfer_buf += data->cmd_bytes;  in mipi_dbi_lcdic_isr()
783 			config->base->CTRL &= ~LCDIC_CTRL_DMA_EN_MASK;  in mipi_dbi_lcdic_isr()
785 		if (data->xfer_bytes == 0) {  in mipi_dbi_lcdic_isr()
787 			base->IMR |= LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_isr()
789 			k_sem_give(&data->xfer_sem);  in mipi_dbi_lcdic_isr()
792 			data->cmd_bytes = MIN(data->xfer_bytes, LCDIC_MAX_XFER);  in mipi_dbi_lcdic_isr()
794 					       data->pixel_fmt,  in mipi_dbi_lcdic_isr()
796 					       data->cmd_bytes);  in mipi_dbi_lcdic_isr()
797 			if (data->cmd_bytes & 0x3) {  in mipi_dbi_lcdic_isr()
801 				data->unaligned_word = mipi_dbi_lcdic_get_unaligned(  in mipi_dbi_lcdic_isr()
802 								data->xfer_buf,  in mipi_dbi_lcdic_isr()
803 								data->cmd_bytes);  in mipi_dbi_lcdic_isr()
806 			if (((((uint32_t)data->xfer_buf) & 0x3) == 0) ||  in mipi_dbi_lcdic_isr()
807 			    (data->cmd_bytes < 4)) {  in mipi_dbi_lcdic_isr()
817 				bytes_written = mipi_dbi_lcdic_fill_tx(base, data->xfer_buf,  in mipi_dbi_lcdic_isr()
818 								       data->cmd_bytes,  in mipi_dbi_lcdic_isr()
819 								       data->unaligned_word);  in mipi_dbi_lcdic_isr()
821 					data->xfer_buf += bytes_written;  in mipi_dbi_lcdic_isr()
822 					data->cmd_bytes -= bytes_written;  in mipi_dbi_lcdic_isr()
823 					data->xfer_bytes -= bytes_written;  in mipi_dbi_lcdic_isr()
831 		bytes_written = mipi_dbi_lcdic_fill_tx(base, data->xfer_buf,  in mipi_dbi_lcdic_isr()
832 						      data->cmd_bytes,  in mipi_dbi_lcdic_isr()
833 						      data->unaligned_word);  in mipi_dbi_lcdic_isr()
835 			data->xfer_buf += bytes_written;  in mipi_dbi_lcdic_isr()
836 			data->cmd_bytes -= bytes_written;  in mipi_dbi_lcdic_isr()
837 			data->xfer_bytes -= bytes_written;  in mipi_dbi_lcdic_isr()