2  * (C) Copyright 2020-2021 SiFive, Inc.
5  * SPDX-License-Identifier: Apache-2.0
8  * https://github.com/sifive/freedom-u540-c000-bootloader
24 #define DRAM_CLASS_DDR4			0xA
25 #define OPTIMAL_RMODW_EN		BIT(0)
34 #define DFI_PHY_RDLVL_GATE_MODE		BIT(0)
36 #define PORT_ADDR_PROTECTION_EN		BIT(0)
41 #define WRLVL_EN			BIT(0)
43 #define PHY_RX_CAL_DQ0_0_OFFSET		0
46 #define DDR_CTL_REG(d, i) (*(d->ddrctl + i))
47 #define DDR_PHY_REG(d, i) (*(d->ddrphy + i))
62 	for (i = 1152; i <= 1214; i++) {  in phy_reset()
65 	for (i = 0; i <= 1151; i++) {  in phy_reset()
74 	for (i = 0; i <= 264; i++) {  in ddr_writeregmap()
82 	return ((DDR_CTL_REG(ddr_ctrl, 0) >> DRAM_CLASS_OFFSET) & 0xF);  in ddr_getdramclass()
87 	uint64_t fails = 0;  in check_errata()
90 	for (bit = 0, dq = 0; bit < 2; bit++, dq++) {  in check_errata()
93 		if (bit == 0) {  in check_errata()
99 		uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;  in check_errata()
100 		uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset + 6)) & 0x3F;  in check_errata()
102 		uint8_t failc0 = ((down == 0) && (up == 0x3F));  in check_errata()
103 		uint8_t failc1 = ((up == 0) && (down == 0x3F));  in check_errata()
107 			if (fails == 0) {  in check_errata()
110 			char slicelsc = '0';  in check_errata()
111 			char slicemsc = '0';  in check_errata()
125 	uint32_t slicebase = 0;  in ddr_phy_fixup()
129 	for (uint32_t slice = 0; slice < 8; slice++) {  in ddr_phy_fixup()
132 		for (uint32_t reg = 0 ; reg < 4; reg++) {  in ddr_phy_fixup()
138 	return (0);  in ddr_phy_fixup()
143 	struct ddr_ctrl_data *ddr_ctrl = dev->data;  in ddr_init()
145 	LOG_DBG("start: 0x%lx", (uintptr_t)ddr_ctrl->ddr_start);  in ddr_init()
146 	LOG_DBG("size:  0x%lx", ddr_ctrl->ddr_size);  in ddr_init()
167 	size_t end_addr_16Kblocks = ((ddr_ctrl->ddr_size >> 14) & 0x7FFFFF) - 1;  in ddr_init()
169 	DDR_CTL_REG(ddr_ctrl, 209) = 0x0;  in ddr_init()
171 	DDR_CTL_REG(ddr_ctrl, 212) = 0x0;  in ddr_init()
172 	DDR_CTL_REG(ddr_ctrl, 214) = 0x0;  in ddr_init()
173 	DDR_CTL_REG(ddr_ctrl, 216) = 0x0;  in ddr_init()
175 	DDR_CTL_REG(ddr_ctrl, 225) = 0xFFFFFFFF;  in ddr_init()
182 	DDR_CTL_REG(ddr_ctrl, 0) |= 1;  in ddr_init()
183 	/* WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 */  in ddr_init()
184 	while ((DDR_CTL_REG(ddr_ctrl, 132) & MC_INIT_COMPLETE) != 0) {  in ddr_init()
188 	uint64_t ddr_end = (uint64_t)ddr_ctrl->ddr_start + ddr_ctrl->ddr_size;  in ddr_init()
191 	volatile uint64_t *filterreg = (volatile uint64_t *)ddr_ctrl->ddr_physical_filter;  in ddr_init()
193 	filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);  in ddr_init()
197 	return 0;  in ddr_init()
203 	.ddrctl = (uint32_t *)DT_REG_ADDR_BY_IDX(DDRCTL_NODE, 0),
211 DEVICE_DT_INST_DEFINE(0, ddr_init, NULL, &ddrctl_private_data, NULL, POST_KERNEL,