79 #define QSPI_DATA_CFG(n)								\  argument
82 			DT_INST_STRING_UPPER_TOKEN(n, data_rate)),			\
83 		.dataAlign = COND_CODE_1(DT_INST_PROP(n, hold_time_2x),			\
88 #define QSPI_ADDR_CFG(n) \  argument
90 		.columnAddr = DT_INST_PROP_OR(n, column_space, 0),			\
91 		.wordAddresable = DT_INST_PROP(n, word_addressable),			\
94 #define QSPI_BYTES_SWAP_ADDR(n)								\  argument
96 		(.byteSwap = DT_INST_PROP(n, byte_swapping),))
98 #define QSPI_SAMPLE_DELAY(n)								\  argument
99 	COND_CODE_1(DT_INST_PROP(n, sample_delay_half_cycle),				\
103 #define QSPI_SAMPLE_PHASE(n)								\  argument
104 	COND_CODE_1(DT_INST_PROP(n, sample_phase_inverted),				\
108 #define QSPI_AHB_BUFFERS(n)								\  argument
110 		.masters = DT_INST_PROP(n, ahb_buffers_masters),			\
111 		.sizes = DT_INST_PROP(n, ahb_buffers_sizes),				\
112 		.allMasters = (bool)DT_INST_PROP(n, ahb_buffers_all_masters),		\
115 #define QSPI_DLL_CFG(n, side, side_upper)						\  argument
119 				DT_INST_STRING_UPPER_TOKEN(n, side##_dll_mode)),	\
120 			.freqEnable = DT_INST_PROP(n, side##_dll_freq_enable),		\
121 			.coarseDelay = DT_INST_PROP(n, side##_dll_coarse_delay),	\
122 			.fineDelay = DT_INST_PROP(n, side##_dll_fine_delay),		\
123 			.tapSelect = DT_INST_PROP(n, side##_dll_tap_select),		\
125 			.referenceCounter = DT_INST_PROP(n, side##_dll_ref_counter),	\
126 			.resolution = DT_INST_PROP(n, side##_dll_resolution),		\
131 #define QSPI_READ_MODE(n, side, side_upper)						\  argument
132 	_CONCAT(QSPI_IP_READ_MODE_, DT_INST_STRING_UPPER_TOKEN(n, side##_rx_clock_source))
134 #define QSPI_IDLE_SIGNAL_DRIVE(n, side, side_upper)					\  argument
136 		.io2IdleValue##side_upper = (uint8_t)DT_INST_PROP(n, side##_io2_idle_high),\
137 		.io3IdleValue##side_upper = (uint8_t)DT_INST_PROP(n, side##_io3_idle_high),\
147 #define QSPI_PORT_SIZE(n, side_upper)							\  argument
148 	DT_INST_FOREACH_CHILD_VARGS(n, QSPI_PORT_SIZE_FN, side_upper, 1)		\
149 	DT_INST_FOREACH_CHILD_VARGS(n, QSPI_PORT_SIZE_FN, side_upper, 2)
151 #define QSPI_SIDE_CFG(n, side, side_upper)						\  argument
152 	QSPI_IDLE_SIGNAL_DRIVE(n, side, side_upper)					\
153 	QSPI_DLL_CFG(n, side, side_upper)						\
154 	QSPI_PORT_SIZE(n, side_upper)							\
155 	.readMode##side_upper = QSPI_READ_MODE(n, side, side_upper),
157 #define MEMC_NXP_S32_QSPI_CONTROLLER_CONFIG(n)						\  argument
158 	BUILD_ASSERT(DT_INST_PROP_LEN(n, ahb_buffers_masters) == QSPI_IP_AHB_BUFFERS,	\
160 	BUILD_ASSERT(DT_INST_PROP_LEN(n, ahb_buffers_sizes) == QSPI_IP_AHB_BUFFERS,	\
163 		_CONCAT(FEATURE_QSPI_, DT_INST_STRING_UPPER_TOKEN(n, a_rx_clock_source)) == 1,\
167 	memc_nxp_s32_qspi_controller_cfg_##n = {					\
168 		.csHoldTime = DT_INST_PROP(n, cs_hold_time),				\
169 		.csSetupTime = DT_INST_PROP(n, cs_setup_time),				\
170 		.sampleDelay = QSPI_SAMPLE_DELAY(n),					\
171 		.samplePhase = QSPI_SAMPLE_PHASE(n),					\
172 		.ahbConfig = QSPI_AHB_BUFFERS(n),					\
173 		QSPI_SIDE_CFG(n, a, A)							\
174 		QSPI_DATA_CFG(n)							\
175 		QSPI_ADDR_CFG(n)							\
176 		QSPI_BYTES_SWAP_ADDR(n)							\
179 #define MEMC_NXP_S32_QSPI_INIT_DEVICE(n)						\  argument
180 	PINCTRL_DT_INST_DEFINE(n);							\
181 	MEMC_NXP_S32_QSPI_CONTROLLER_CONFIG(n);						\
182 	static struct memc_nxp_s32_qspi_data memc_nxp_s32_qspi_data_##n;		\
183 	static const struct memc_nxp_s32_qspi_config memc_nxp_s32_qspi_config_##n = {	\
184 		.base = (QuadSPI_Type *)DT_INST_REG_ADDR(n),				\
185 		.controller_cfg = &memc_nxp_s32_qspi_controller_cfg_##n,		\
186 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),				\
188 	DEVICE_DT_INST_DEFINE(n,							\
191 		&memc_nxp_s32_qspi_data_##n,						\
192 		&memc_nxp_s32_qspi_config_##n,						\