4  * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/qspi/nxp-s32-qspi.h>
53 	const struct memc_nxp_s32_qspi_config *config = dev->config;  in memc_nxp_s32_qspi_init()
54 	struct memc_nxp_s32_qspi_data *data = dev->data;  in memc_nxp_s32_qspi_init()
57 	data->instance = get_instance(config->base);  in memc_nxp_s32_qspi_init()
59 	if (pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT)) {  in memc_nxp_s32_qspi_init()
60 		return -EIO;  in memc_nxp_s32_qspi_init()
63 	status = Qspi_Ip_ControllerInit(data->instance, config->controller_cfg);  in memc_nxp_s32_qspi_init()
66 			data->instance, status);  in memc_nxp_s32_qspi_init()
67 		return -EIO;  in memc_nxp_s32_qspi_init()
75 	struct memc_nxp_s32_qspi_data *data = dev->data;  in memc_nxp_s32_qspi_get_instance()
77 	return data->instance;  in memc_nxp_s32_qspi_get_instance()
80 #define QSPI_DATA_CFG(n)								\  argument
83 			DT_INST_STRING_UPPER_TOKEN(n, data_rate)),			\
84 		.dataAlign = COND_CODE_1(DT_INST_PROP(n, hold_time_2x),			\
89 #define QSPI_ADDR_CFG(n) \  argument
91 		.columnAddr = DT_INST_PROP_OR(n, column_space, 0),			\
92 		.wordAddresable = DT_INST_PROP(n, word_addressable),			\
95 #define QSPI_BYTES_SWAP_ADDR(n)								\  argument
97 		(.byteSwap = DT_INST_PROP(n, byte_swapping),))
99 #define QSPI_SAMPLE_DELAY(n)								\  argument
100 	COND_CODE_1(DT_INST_PROP(n, sample_delay_half_cycle),				\
104 #define QSPI_SAMPLE_PHASE(n)								\  argument
105 	COND_CODE_1(DT_INST_PROP(n, sample_phase_inverted),				\
109 #define QSPI_AHB_BUFFERS(n)								\  argument
111 		.masters = DT_INST_PROP(n, ahb_buffers_masters),			\
112 		.sizes = DT_INST_PROP(n, ahb_buffers_sizes),				\
113 		.allMasters = (bool)DT_INST_PROP(n, ahb_buffers_all_masters),		\
116 #define QSPI_DLL_CFG(n, side, side_upper)						\  argument
120 				DT_INST_STRING_UPPER_TOKEN(n, side##_dll_mode)),	\
121 			.freqEnable = DT_INST_PROP(n, side##_dll_freq_enable),		\
122 			.coarseDelay = DT_INST_PROP(n, side##_dll_coarse_delay),	\
123 			.fineDelay = DT_INST_PROP(n, side##_dll_fine_delay),		\
124 			.tapSelect = DT_INST_PROP(n, side##_dll_tap_select),		\
126 			.referenceCounter = DT_INST_PROP(n, side##_dll_ref_counter),	\
127 			.resolution = DT_INST_PROP(n, side##_dll_resolution),		\
132 #define QSPI_READ_MODE(n, side, side_upper)						\  argument
133 	_CONCAT(QSPI_IP_READ_MODE_, DT_INST_STRING_UPPER_TOKEN(n, side##_rx_clock_source))
135 #define QSPI_IDLE_SIGNAL_DRIVE(n, side, side_upper)					\  argument
137 		.io2IdleValue##side_upper = (uint8_t)DT_INST_PROP(n, side##_io2_idle_high),\
138 		.io3IdleValue##side_upper = (uint8_t)DT_INST_PROP(n, side##_io3_idle_high),\
148 #define QSPI_PORT_SIZE(n, side_upper)							\  argument
149 	DT_INST_FOREACH_CHILD_VARGS(n, QSPI_PORT_SIZE_FN, side_upper, 1)		\
150 	DT_INST_FOREACH_CHILD_VARGS(n, QSPI_PORT_SIZE_FN, side_upper, 2)
152 #define QSPI_SIDE_CFG(n, side, side_upper)						\  argument
153 	QSPI_IDLE_SIGNAL_DRIVE(n, side, side_upper)					\
154 	QSPI_DLL_CFG(n, side, side_upper)						\
155 	QSPI_PORT_SIZE(n, side_upper)							\
156 	.readMode##side_upper = QSPI_READ_MODE(n, side, side_upper),
161 #define SFP_MDAD_NODE(n) DT_INST_CHILD(n, sfp_mdad)  argument
170 #define _QSPI_SFP_MDAD_CFG(node_id, n)							\  argument
179 #define QSPI_SFP_MDAD_CFG(n)								\  argument
181 		DT_FOREACH_CHILD_STATUS_OKAY_VARGS(SFP_MDAD_NODE(n), _QSPI_SFP_MDAD_CFG, n)\
186 #define SFP_FRAD_NODE(n) DT_INST_CHILD(n, sfp_frad)  argument
204 #define _QSPI_SFP_FRAD_CFG(node_id, n)							\  argument
207 		.EndAddress = DT_REG_ADDR(node_id) + DT_REG_SIZE(node_id) - 1,		\
215 #define QSPI_SFP_FRAD_CFG(n)								\  argument
217 		DT_FOREACH_CHILD_STATUS_OKAY_VARGS(SFP_FRAD_NODE(n), _QSPI_SFP_FRAD_CFG, n)\
223 #define QSPI_SFP_CFG(n)									\  argument
227 			IF_ENABLED(QSPI_IP_SFP_ENABLE_MDAD, (QSPI_SFP_MDAD_CFG(n)))	\
228 			IF_ENABLED(QSPI_IP_SFP_ENABLE_FRAD, (QSPI_SFP_FRAD_CFG(n)))	\
233 #define MEMC_NXP_S32_QSPI_CONTROLLER_CONFIG(n)						\  argument
234 	BUILD_ASSERT(DT_INST_PROP_LEN(n, ahb_buffers_masters) == QSPI_IP_AHB_BUFFERS,	\
235 		"ahb-buffers-masters must be of size QSPI_IP_AHB_BUFFERS");		\
236 	BUILD_ASSERT(DT_INST_PROP_LEN(n, ahb_buffers_sizes) == QSPI_IP_AHB_BUFFERS,	\
237 		"ahb-buffers-sizes must be of size QSPI_IP_AHB_BUFFERS");		\
239 		_CONCAT(FEATURE_QSPI_, DT_INST_STRING_UPPER_TOKEN(n, a_rx_clock_source)) == 1,\
240 		"a-rx-clock-source source mode selected is not supported");		\
243 	memc_nxp_s32_qspi_controller_cfg_##n = {					\
244 		.csHoldTime = DT_INST_PROP(n, cs_hold_time),				\
245 		.csSetupTime = DT_INST_PROP(n, cs_setup_time),				\
246 		.sampleDelay = QSPI_SAMPLE_DELAY(n),					\
247 		.samplePhase = QSPI_SAMPLE_PHASE(n),					\
248 		.ahbConfig = QSPI_AHB_BUFFERS(n),					\
249 		QSPI_SIDE_CFG(n, a, A)							\
250 		QSPI_DATA_CFG(n)							\
251 		QSPI_ADDR_CFG(n)							\
252 		QSPI_BYTES_SWAP_ADDR(n)							\
253 		IF_ENABLED(FEATURE_QSPI_HAS_SFP, (QSPI_SFP_CFG(n)))			\
256 #define MEMC_NXP_S32_QSPI_INIT_DEVICE(n)						\  argument
257 	PINCTRL_DT_INST_DEFINE(n);							\
258 	MEMC_NXP_S32_QSPI_CONTROLLER_CONFIG(n);						\
259 	static struct memc_nxp_s32_qspi_data memc_nxp_s32_qspi_data_##n;		\
260 	static const struct memc_nxp_s32_qspi_config memc_nxp_s32_qspi_config_##n = {	\
261 		.base = (QuadSPI_Type *)DT_INST_REG_ADDR(n),				\
262 		.controller_cfg = &memc_nxp_s32_qspi_controller_cfg_##n,		\
263 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),				\
265 	DEVICE_DT_INST_DEFINE(n,							\
268 		&memc_nxp_s32_qspi_data_##n,						\
269 		&memc_nxp_s32_qspi_config_##n,						\