4  * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
9 #include <zephyr/devicetree.h>
10 #include <zephyr/init.h>
11 #include <zephyr/sys/util.h>
13 #include <zephyr/irq.h>
89 static FLEXRAM_Type *const base = (FLEXRAM_Type *) DT_REG_ADDR(FLEXRAM_DT_NODE);
110 	if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) {  in nxp_flexram_isr()
111 		base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK;  in nxp_flexram_isr()
114 	if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) {  in nxp_flexram_isr()
115 		base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK;  in nxp_flexram_isr()
118 	if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) {  in nxp_flexram_isr()
119 		base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK;  in nxp_flexram_isr()
125 	if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) {  in nxp_flexram_isr()
126 		base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK;  in nxp_flexram_isr()
129 	if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) {  in nxp_flexram_isr()
130 		base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK;  in nxp_flexram_isr()
133 	if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) {  in nxp_flexram_isr()
134 		base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK;  in nxp_flexram_isr()
144 	ocram_addr -= DT_REG_ADDR(OCRAM_DT_NODE);  in memc_flexram_set_ocram_magic_addr()
146 		return -EINVAL;  in memc_flexram_set_ocram_magic_addr()
149 	base->OCRAM_MAGIC_ADDR &= ~FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK;  in memc_flexram_set_ocram_magic_addr()
150 	base->OCRAM_MAGIC_ADDR |= FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(ocram_addr);  in memc_flexram_set_ocram_magic_addr()
152 	base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK;  in memc_flexram_set_ocram_magic_addr()
155 	return -ENODEV;  in memc_flexram_set_ocram_magic_addr()
162 	itcm_addr -= DT_REG_ADDR(ITCM_DT_NODE);  in memc_flexram_set_itcm_magic_addr()
164 		return -EINVAL;  in memc_flexram_set_itcm_magic_addr()
167 	base->ITCM_MAGIC_ADDR &= ~FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK;  in memc_flexram_set_itcm_magic_addr()
168 	base->ITCM_MAGIC_ADDR |= FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(itcm_addr);  in memc_flexram_set_itcm_magic_addr()
170 	base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK;  in memc_flexram_set_itcm_magic_addr()
173 	return -ENODEV;  in memc_flexram_set_itcm_magic_addr()
180 	dtcm_addr -= DT_REG_ADDR(DTCM_DT_NODE);  in memc_flexram_set_dtcm_magic_addr()
182 		return -EINVAL;  in memc_flexram_set_dtcm_magic_addr()
185 	base->DTCM_MAGIC_ADDR &= ~FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK;  in memc_flexram_set_dtcm_magic_addr()
186 	base->DTCM_MAGIC_ADDR |= FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(dtcm_addr);  in memc_flexram_set_dtcm_magic_addr()
188 	base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK;  in memc_flexram_set_dtcm_magic_addr()
191 	return -ENODEV;  in memc_flexram_set_dtcm_magic_addr()
201 		base->TCM_CTRL |= FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;  in nxp_flexram_init()
204 		base->TCM_CTRL |= FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;  in nxp_flexram_init()
208 	base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK;  in nxp_flexram_init()
209 	base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK;  in nxp_flexram_init()
210 	base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK;  in nxp_flexram_init()
211 	base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK;  in nxp_flexram_init()
212 	base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK;  in nxp_flexram_init()
213 	base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK;  in nxp_flexram_init()
217 	base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK;  in nxp_flexram_init()
218 	base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK;  in nxp_flexram_init()
219 	base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK;  in nxp_flexram_init()