2  * Copyright 2023-2024 NXP
4  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/net/mdio.h>
12 #include <zephyr/drivers/mdio.h>
36  * in order to wait for the completion of an MDIO transaction.
37  * It returns -ETIMEDOUT if timeout occurs as specified in DT,
39  * operation, otherwise -EIO.
43 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_wait_xfer()
47 		return -EWOULDBLOCK;  in nxp_enet_mdio_wait_xfer()
50 	if (!data->interrupt_up) {  in nxp_enet_mdio_wait_xfer()
53 		k_sem_give(&data->mdio_sem);  in nxp_enet_mdio_wait_xfer()
56 	/* Wait for the MDIO transaction to finish or time out */  in nxp_enet_mdio_wait_xfer()
57 	k_sem_take(&data->mdio_sem, K_USEC(CONFIG_MDIO_NXP_ENET_TIMEOUT));  in nxp_enet_mdio_wait_xfer()
62 /* MDIO Read API implementation */
66 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_read()
69 	/* Only one MDIO bus operation attempt at a time */  in nxp_enet_mdio_read()
70 	(void)k_mutex_lock(&data->mdio_mutex, K_FOREVER);  in nxp_enet_mdio_read()
73 	 * Clear the bit (W1C) that indicates MDIO transfer is ready to  in nxp_enet_mdio_read()
76 	data->base->EIR = ENET_EIR_MII_MASK;  in nxp_enet_mdio_read()
79 	 * Write MDIO frame to MII management register which will  in nxp_enet_mdio_read()
80 	 * send the read command and data out to the MDIO bus as this frame:  in nxp_enet_mdio_read()
83 	 * PA = PHY/Port address  in nxp_enet_mdio_read()
86 	 * data = data to be written to the PHY register  in nxp_enet_mdio_read()
88 	data->base->MMFR = ENET_MMFR_ST(0x1U) |  in nxp_enet_mdio_read()
96 		(void)k_mutex_unlock(&data->mdio_mutex);  in nxp_enet_mdio_read()
101 	*read_data = (data->base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT;  in nxp_enet_mdio_read()
104 	data->base->EIR = ENET_EIR_MII_MASK;  in nxp_enet_mdio_read()
106 	/* This MDIO interaction is finished */  in nxp_enet_mdio_read()
107 	(void)k_mutex_unlock(&data->mdio_mutex);  in nxp_enet_mdio_read()
112 /* MDIO Write API implementation */
116 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_write()
119 	/* Only one MDIO bus operation attempt at a time */  in nxp_enet_mdio_write()
120 	(void)k_mutex_lock(&data->mdio_mutex, K_FOREVER);  in nxp_enet_mdio_write()
123 	 * Clear the bit (W1C) that indicates MDIO transfer is ready to  in nxp_enet_mdio_write()
126 	data->base->EIR = ENET_EIR_MII_MASK;  in nxp_enet_mdio_write()
129 	 * Write MDIO frame to MII management register which will  in nxp_enet_mdio_write()
130 	 * send the write command and data out to the MDIO bus as this frame:  in nxp_enet_mdio_write()
133 	 * PA = PHY/Port address  in nxp_enet_mdio_write()
136 	 * data = data to be written to the PHY register  in nxp_enet_mdio_write()
138 	data->base->MMFR = ENET_MMFR_ST(0x1U) |  in nxp_enet_mdio_write()
147 		(void)k_mutex_unlock(&data->mdio_mutex);  in nxp_enet_mdio_write()
152 	data->base->EIR = ENET_EIR_MII_MASK;  in nxp_enet_mdio_write()
154 	/* This MDIO interaction is finished */  in nxp_enet_mdio_write()
155 	(void)k_mutex_unlock(&data->mdio_mutex);  in nxp_enet_mdio_write()
160 static DEVICE_API(mdio, nxp_enet_mdio_api) = {
167 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_isr_cb()
169 	data->base->EIR = ENET_EIR_MII_MASK;  in nxp_enet_mdio_isr_cb()
171 	k_sem_give(&data->mdio_sem);  in nxp_enet_mdio_isr_cb()
176 	const struct nxp_enet_mdio_config *config = dev->config;  in nxp_enet_mdio_post_module_reset_init()
177 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_post_module_reset_init()
181 	(void) clock_control_get_rate(config->clock_dev, config->clock_subsys,  in nxp_enet_mdio_post_module_reset_init()
183 	uint32_t mii_speed = (enet_module_clock_rate + 2 * config->mdc_freq - 1) /  in nxp_enet_mdio_post_module_reset_init()
184 					(2 * config->mdc_freq) - 1;  in nxp_enet_mdio_post_module_reset_init()
185 	uint32_t holdtime = (10 + NSEC_PER_SEC / enet_module_clock_rate - 1) /  in nxp_enet_mdio_post_module_reset_init()
186 					(NSEC_PER_SEC / enet_module_clock_rate) - 1;  in nxp_enet_mdio_post_module_reset_init()
188 			(config->disable_preamble ? ENET_MSCR_DIS_PRE_MASK : 0);  in nxp_enet_mdio_post_module_reset_init()
189 	data->base->MSCR = mscr;  in nxp_enet_mdio_post_module_reset_init()
195 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_callback()
208 		data->interrupt_up = true;  in nxp_enet_mdio_callback()
209 		data->base->EIMR |= ENET_EIMR_MII_MASK;  in nxp_enet_mdio_callback()
218 	const struct nxp_enet_mdio_config *config = dev->config;  in nxp_enet_mdio_init()
219 	struct nxp_enet_mdio_data *data = dev->data;  in nxp_enet_mdio_init()
222 	data->base = (ENET_Type *)DEVICE_MMIO_GET(config->module_dev);  in nxp_enet_mdio_init()
224 	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);  in nxp_enet_mdio_init()
229 	ret = k_mutex_init(&data->mdio_mutex);  in nxp_enet_mdio_init()
234 	ret = k_sem_init(&data->mdio_sem, 0, 1);  in nxp_enet_mdio_init()
239 	/* All operations done after module reset should be done during device init too */  in nxp_enet_mdio_init()