Lines Matching refs:reg_addr
61 mem_addr_t reg_addr = (mem_addr_t)(ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_MODE_OFST); in dwxgmac_software_reset() local
63 sys_write32(DMA_MODE_SWR_SET(1u), reg_addr); in dwxgmac_software_reset()
65 ret = WAIT_FOR(!(sys_read32(reg_addr) & DMA_MODE_SWR_SET_MSK), delay_us, k_msleep(1)); in dwxgmac_software_reset()
73 static inline int mdio_busy_wait(uint32_t reg_addr, uint32_t bit_msk) in mdio_busy_wait() argument
78 ret = WAIT_FOR(!(sys_read32(reg_addr) & bit_msk), delay_us, k_msleep(1)); in mdio_busy_wait()
94 uint32_t reg_addr; in mdio_transfer() local
107 reg_addr = ioaddr + CORE_MDIO_CLAUSE_22_PORT_OFST; in mdio_transfer()
108 reg_data = sys_read32(reg_addr); in mdio_transfer()
110 sys_write32(reg_data, reg_addr); in mdio_transfer()
112 reg_addr = ioaddr + CORE_MDIO_SINGLE_COMMAND_ADDRESS_OFST; in mdio_transfer()
115 sys_write32(mdio_addr, reg_addr); in mdio_transfer()
117 reg_addr = ioaddr + CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_OFST; in mdio_transfer()
125 sys_write32(mdio_data, reg_addr); in mdio_transfer()
127 retval = mdio_busy_wait(reg_addr, CORE_MDIO_SINGLE_COMMAND_CONTROL_DATA_SBUSY_SET_MSK); in mdio_transfer()
134 sys_read32(reg_addr)); in mdio_transfer()