Lines Matching +full:- +full:n
2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
43 const struct nxp_s32_mru_config *cfg = dev->config; in is_rx_channel_valid()
45 return ((ch < MRU_MAX_CHANNELS) && (ch < cfg->hw_cfg.NumChannel)); in is_rx_channel_valid()
52 const struct nxp_s32_mru_config *cfg = dev->config; in get_mbox_addr()
54 return ((uintptr_t)cfg->base + (channel + 1) * MRU_CHANNEL_OFFSET in get_mbox_addr()
61 const struct nxp_s32_mru_config *cfg = dev->config; in nxp_s32_mru_send()
67 return -EINVAL; in nxp_s32_mru_send()
71 return -EINVAL; in nxp_s32_mru_send()
72 } else if (msg->size > (MRU_MBOX_SIZE * MRU_MAX_MBOX_PER_CHAN)) { in nxp_s32_mru_send()
73 return -EMSGSIZE; in nxp_s32_mru_send()
81 tx_cfg.LastTxMBIndex = MRU_MAX_MBOX_PER_CHAN - 1; in nxp_s32_mru_send()
83 tx_cfg.ChMBSTATAdd = (volatile uint32 *)&cfg->base->CHXCONFIG[channel].CH_MBSTAT; in nxp_s32_mru_send()
85 status = Mru_Ip_Transmit(&tx_cfg, (const uint32 *)msg->data); in nxp_s32_mru_send()
87 return (status == MRU_IP_STATUS_SUCCESS ? 0 : -EBUSY); in nxp_s32_mru_send()
93 struct nxp_s32_mru_data *data = dev->data; in nxp_s32_mru_register_callback()
96 return -EINVAL; in nxp_s32_mru_register_callback()
99 data->cb[channel] = cb; in nxp_s32_mru_register_callback()
100 data->user_data[channel] = user_data; in nxp_s32_mru_register_callback()
118 struct nxp_s32_mru_data *data = dev->data; in nxp_s32_mru_set_enabled()
119 const struct nxp_s32_mru_config *cfg = dev->config; in nxp_s32_mru_set_enabled()
121 const Mru_Ip_ChannelCfgType *ch_cfg = cfg->hw_cfg.ChannelCfg; in nxp_s32_mru_set_enabled()
124 return -EINVAL; in nxp_s32_mru_set_enabled()
127 if (enable && (data->cb[channel] == NULL)) { in nxp_s32_mru_set_enabled()
128 LOG_WRN("Enabling channel without a registered callback\n"); in nxp_s32_mru_set_enabled()
154 const struct nxp_s32_mru_config *cfg = dev->config; in nxp_s32_mru_init()
156 if (cfg->hw_cfg.NumChannel == 0) { in nxp_s32_mru_init()
162 Mru_Ip_Init(&cfg->hw_cfg); in nxp_s32_mru_init()
168 cfg->config_irq(); in nxp_s32_mru_init()
175 const struct nxp_s32_mru_config *config = dev->config; in nxp_s32_mru_isr()
177 Mru_Ip_IrqHandler(config->hw_cfg.InstanceId, config->irq_group); in nxp_s32_mru_isr()
188 #define MRU_BASE(n) ((RTU_MRU_Type *)DT_INST_REG_ADDR(n)) argument
189 #define MRU_RX_CHANNELS(n) DT_INST_PROP_OR(n, rx_channels, 0) argument
190 #define MRU_MBOX_ADDR(n, ch, mb) \ argument
191 (DT_INST_REG_ADDR(n) + ((ch + 1) * MRU_CHANNEL_OFFSET) + (MRU_MBOX_SIZE * mb))
193 #define MRU_HW_INSTANCE_CHECK(i, n) \ argument
194 ((DT_INST_REG_ADDR(n) == IP_MRU_##i##_BASE) ? i : 0)
196 #define MRU_HW_INSTANCE(n) \ argument
197 LISTIFY(__DEBRACKET RTU_MRU_INSTANCE_COUNT, MRU_HW_INSTANCE_CHECK, (|), n)
199 #define MRU_INIT_IRQ_FUNC(n) \ argument
200 static void nxp_s32_mru_##n##_init_irq(void) \
202 IRQ_CONNECT(DT_INST_IRQN(n), \
203 DT_INST_IRQ(n, priority), \
205 DEVICE_DT_INST_GET(n), \
206 DT_INST_IRQ(n, flags)); \
207 irq_enable(DT_INST_IRQN(n)); \
210 #define MRU_CH_RX_CFG(i, n) \ argument
212 nxp_s32_mru_##n##_ch_##i##_rx_mbox_addr[MRU_MAX_MBOX_PER_CHAN] = { \
213 (uint32 *const)MRU_MBOX_ADDR(n, i, 0), \
215 static uint32 nxp_s32_mru_##n##_ch_##i##_buf[MRU_MAX_MBOX_PER_CHAN]; \
216 static const Mru_Ip_ReceiveChannelType nxp_s32_mru_##n##_ch_##i##_rx_cfg = { \
220 .MBAddList = nxp_s32_mru_##n##_ch_##i##_rx_mbox_addr, \
221 .RxBuffer = nxp_s32_mru_##n##_ch_##i##_buf, \
222 .ReceiveNotification = nxp_s32_mru_##n##_cb \
225 #define MRU_CH_RX_LINK_CFG_MBOX(i, n, chan, intgroup) \ argument
227 [intgroup] = { &nxp_s32_mru_##n##_ch_##chan##_rx_cfg } \
230 #define MRU_CH_RX_LINK_CFG(i, n) \ argument
232 nxp_s32_mru_##n##_ch_##i##_rx_link_cfg[MRU_MAX_MBOX_PER_CHAN][MRU_MAX_INT_GROUPS] = {\
233 MRU_CH_RX_LINK_CFG_MBOX(0, n, i, MRU_INT_GROUP(DT_INST_IRQN(n))) \
236 #define MRU_CH_CFG(i, n) \ argument
238 .ChCFG0Add = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_CFG0, \
240 .ChCFG1Add = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_CFG1, \
241 .ChCFG1 = RTU_MRU_CH_CFG1_MBIC0(MRU_INT_GROUP(DT_INST_IRQN(n))), \
242 .ChMBSTATAdd = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_MBSTAT, \
244 .MBLinkReceiveChCfg = nxp_s32_mru_##n##_ch_##i##_rx_link_cfg \
248 #define MRU_CALLBACK_WRAPPER_FUNC(n) \ argument
249 void nxp_s32_mru_##n##_cb(uint8_t channel, const uint32 *buf, uint8_t mbox_count) \
251 const struct device *dev = DEVICE_DT_INST_GET(n); \
252 struct nxp_s32_mru_data *data = dev->data; \
255 if (data->cb[channel] != NULL) { \
260 data->cb[channel](dev, channel, data->user_data[channel], &msg);\
265 #define MRU_CH_RX_DEFINITIONS(n) \ argument
266 MRU_CALLBACK_WRAPPER_FUNC(n) \
267 MRU_INIT_IRQ_FUNC(n) \
268 LISTIFY(MRU_RX_CHANNELS(n), MRU_CH_RX_CFG, (;), n); \
269 LISTIFY(MRU_RX_CHANNELS(n), MRU_CH_RX_LINK_CFG, (;), n); \
270 static const Mru_Ip_ChannelCfgType nxp_s32_mru_##n##_ch_cfg[] = { \
271 LISTIFY(MRU_RX_CHANNELS(n), MRU_CH_CFG, (,), n) \
274 #define MRU_INSTANCE_DEFINE(n) \ argument
275 COND_CODE_0(MRU_RX_CHANNELS(n), (EMPTY), (MRU_CH_RX_DEFINITIONS(n))); \
276 static struct nxp_s32_mru_data nxp_s32_mru_##n##_data; \
277 static struct nxp_s32_mru_config nxp_s32_mru_##n##_config = { \
278 .base = MRU_BASE(n), \
280 .InstanceId = MRU_HW_INSTANCE(n), \
281 .StateIndex = n, \
282 .NumChannel = MRU_RX_CHANNELS(n), \
283 .ChannelCfg = COND_CODE_0(MRU_RX_CHANNELS(n), \
284 (NULL), (nxp_s32_mru_##n##_ch_cfg)), \
286 (const volatile uint32 *)&MRU_BASE(n)->NOTIFY[0], \
287 (const volatile uint32 *)&MRU_BASE(n)->NOTIFY[1] \
290 .irq_group = MRU_INT_GROUP(DT_INST_IRQN(n)), \
291 .config_irq = COND_CODE_0(MRU_RX_CHANNELS(n), \
292 (NULL), (nxp_s32_mru_##n##_init_irq)), \
295 DEVICE_DT_INST_DEFINE(n, nxp_s32_mru_init, NULL, \
296 &nxp_s32_mru_##n##_data, &nxp_s32_mru_##n##_config, \