Lines Matching defs:ipm_mhu_reg_map_t

24 struct ipm_mhu_reg_map_t {  struct
26 	volatile uint32_t cpu0intr_stat;
27 	volatile uint32_t cpu0intr_set;  /* ( /W) CPU 0 Interrupt Set Register */
28 	volatile uint32_t cpu0intr_clr;  /* ( /W) CPU 0 Interrupt Clear Register */
29 	volatile uint32_t reserved0;
31 	volatile uint32_t cpu1intr_stat;
32 	volatile uint32_t cpu1intr_set;  /* ( /W) CPU 1 Interrupt Set Register */
33 	volatile uint32_t cpu1intr_clr;  /* ( /W) CPU 1 Interrupt Clear Register */
34 	volatile uint32_t reserved1[1004];
35 	volatile uint32_t pidr4;         /* ( /W) Peripheral ID 4 */
36 	volatile uint32_t reserved2[3];
37 	volatile uint32_t pidr0;         /* ( /W) Peripheral ID 0 */
38 	volatile uint32_t pidr1;         /* ( /W) Peripheral ID 1 */
39 	volatile uint32_t pidr2;         /* ( /W) Peripheral ID 2 */
40 	volatile uint32_t pidr3;         /* ( /W) Peripheral ID 3 */
41 	volatile uint32_t cidr0;         /* ( /W) Component ID 0 */
42 	volatile uint32_t cidr1;         /* ( /W) Component ID 1 */
43 	volatile uint32_t cidr2;         /* ( /W) Component ID 2 */
44 	volatile uint32_t cidr3;         /* ( /W) Component ID 3 */