121 INTC_PLIC_STATIC_INLINE uint32_t local_irq_to_reg_index(uint32_t local_irq)  in local_irq_to_reg_index()  argument
123 	return local_irq >> LOG2(PLIC_REG_SIZE);  in local_irq_to_reg_index()
126 INTC_PLIC_STATIC_INLINE uint32_t local_irq_to_reg_offset(uint32_t local_irq)  in local_irq_to_reg_offset()  argument
128 	return local_irq_to_reg_index(local_irq) * sizeof(uint32_t);  in local_irq_to_reg_offset()
145 static ALWAYS_INLINE uint32_t get_irq_cpumask(const struct device *dev, uint32_t local_irq)  in get_irq_cpumask()  argument
150 	return data->irq_cpumask[local_irq];  in get_irq_cpumask()
153 	ARG_UNUSED(local_irq);  in get_irq_cpumask()
199 static ALWAYS_INLINE uint32_t local_irq_to_irq(const struct device *dev, uint32_t local_irq)  in local_irq_to_irq()  argument
203 	return irq_to_level_2(local_irq) | config->irq;  in local_irq_to_irq()
207 static inline mem_addr_t get_pending_reg(const struct device *dev, uint32_t local_irq)  in get_pending_reg()  argument
211 	return config->pend + local_irq_to_reg_offset(local_irq);  in get_pending_reg()
244 static uint32_t riscv_plic_irq_trig_val(const struct device *dev, uint32_t local_irq)  in riscv_plic_irq_trig_val()  argument
247 	mem_addr_t trig_addr = config->trig + local_irq_to_reg_offset(local_irq);  in riscv_plic_irq_trig_val()
248 	uint32_t offset = local_irq * CONFIG_PLIC_TRIG_TYPE_BITWIDTH;  in riscv_plic_irq_trig_val()
257 	const uint32_t local_irq = irq_from_level_2(irq);  in plic_irq_enable_set_state()  local
261 			get_context_en_addr(dev, cpu_num) + local_irq_to_reg_offset(local_irq);  in plic_irq_enable_set_state()
265 		WRITE_BIT(en_value, local_irq & PLIC_REG_MASK,  in plic_irq_enable_set_state()
266 			  enable ? (get_irq_cpumask(dev, local_irq) & BIT(cpu_num)) != 0 : false);  in plic_irq_enable_set_state()
314 static int local_irq_is_enabled(const struct device *dev, uint32_t local_irq)  in local_irq_is_enabled()  argument
316 	uint32_t bit_position = local_irq & PLIC_REG_MASK;  in local_irq_is_enabled()
321 			get_context_en_addr(dev, cpu_num) + local_irq_to_reg_offset(local_irq);  in local_irq_is_enabled()
346 	const uint32_t local_irq = irq_from_level_2(irq);  in riscv_plic_irq_is_enabled()  local
350 		ret = local_irq_is_enabled(dev, local_irq);  in riscv_plic_irq_is_enabled()
370 	const uint32_t local_irq = irq_from_level_2(irq);  in riscv_plic_set_priority()  local
371 	mem_addr_t prio_addr = config->prio + (local_irq * sizeof(uint32_t));  in riscv_plic_set_priority()
384 	const uint32_t local_irq = irq_from_level_2(irq);  in riscv_plic_irq_set_pending()  local
385 	mem_addr_t pend_addr = get_pending_reg(dev, local_irq);  in riscv_plic_irq_set_pending()
388 	WRITE_BIT(pend_value, local_irq & PLIC_REG_MASK, true);  in riscv_plic_irq_set_pending()
432 	const uint32_t local_irq = irq_from_level_2(irq);  in riscv_plic_irq_set_affinity()  local
435 	if (local_irq >= config->nr_irqs) {  in riscv_plic_irq_set_affinity()
436 		__ASSERT(false, "overflow: irq %d, local_irq %d", irq, local_irq);  in riscv_plic_irq_set_affinity()
447 	data->irq_cpumask[local_irq] = (plic_cpumask_t)cpumask;  in riscv_plic_irq_set_affinity()
450 	if (local_irq_is_enabled(dev, local_irq)) {  in riscv_plic_irq_set_affinity()
469 						     uint32_t local_irq)  in get_irq_hit_count_cpu()  argument
473 	uint32_t offset = local_irq;  in get_irq_hit_count_cpu()
476 		offset = cpu * config->nr_irqs + local_irq;  in get_irq_hit_count_cpu()
482 static ALWAYS_INLINE uint16_t *get_irq_hit_count_total(const struct device *dev, uint32_t local_irq)  in get_irq_hit_count_total()  argument
486 	uint32_t offset = local_irq;  in get_irq_hit_count_total()
489 		offset = arch_num_cpus() * config->nr_irqs + local_irq;  in get_irq_hit_count_total()
503 	const uint32_t local_irq = sys_read32(claim_complete_addr);  in plic_irq_handler()  local
506 	uint16_t *cpu_count = get_irq_hit_count_cpu(dev, cpu_id, local_irq);  in plic_irq_handler()
507 	uint16_t *total_count = get_irq_hit_count_total(dev, local_irq);  in plic_irq_handler()
526 	if ((CONFIG_MP_MAX_NUM_CPUS > 1) && (local_irq == 0U)) {  in plic_irq_handler()
536 	save_irq[cpu_id] = local_irq;  in plic_irq_handler()
543 	if ((local_irq == 0U) || (local_irq >= config->nr_irqs)) {  in plic_irq_handler()
548 	uint32_t trig_val = riscv_plic_irq_trig_val(dev, local_irq);  in plic_irq_handler()
554 		sys_write32(local_irq, claim_complete_addr);  in plic_irq_handler()
559 	ite = &config->isr_table[local_irq];  in plic_irq_handler()
570 		sys_write32(local_irq, claim_complete_addr);  in plic_irq_handler()
573 	sys_write32(local_irq, claim_complete_addr);  in plic_irq_handler()
725 	uint32_t local_irq, irq, mask;  in cmd_affinity_set()  local
734 	local_irq = (uint32_t)shell_strtol(argv[2], 10, &rc);  in cmd_affinity_set()
739 	if (local_irq >= config->nr_irqs) {  in cmd_affinity_set()
740 		shell_error(sh, "local_irq (%d) > nr_irqs (%d)", local_irq, config->nr_irqs);  in cmd_affinity_set()
754 	if (local_irq != 0) {  in cmd_affinity_set()
755 		irq = local_irq_to_irq(dev, local_irq);  in cmd_affinity_set()
757 		shell_print(sh, "IRQ %d affinity set to 0x%X", local_irq, mask);  in cmd_affinity_set()
759 		for (local_irq = 1; local_irq <= config->nr_irqs; local_irq++) {  in cmd_affinity_set()
760 			irq = local_irq_to_irq(dev, local_irq);  in cmd_affinity_set()
783 		for (uint32_t local_irq = 0; local_irq < config->nr_irqs; local_irq++) {  in cmd_affinity_get()  local
784 			shell_print(sh, "%4d  0x%X", local_irq, get_irq_cpumask(dev, local_irq));  in cmd_affinity_get()
787 		uint32_t local_irq = (uint32_t)shell_strtol(argv[2], 10, &rc);  in cmd_affinity_get()  local
793 		if (local_irq >= config->nr_irqs) {  in cmd_affinity_get()
794 			shell_error(sh, "local_irq (%d) > nr_irqs (%d)", local_irq,  in cmd_affinity_get()
799 		shell_print(sh, "%4d  0x%X", local_irq, get_irq_cpumask(dev, local_irq));  in cmd_affinity_get()