Lines Matching +full:1 +full:b
23 uint8_t _reserved0 : 1;
27 uint8_t _reserved2 : 1;
28 } b; member
41 } b; member
52 uint8_t IP : 1;
54 } b; member
61 uint8_t IE : 1;
63 } b; member
69 /** 0: non-vectored 1:vectored */
70 uint8_t shv : 1;
71 /** 0: level 1: rising edge 2: falling edge */
75 } b; member
90 #define ECLIC_INFO (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1))))
108 return ((1 << len) - 1) & 0xFFFFU; in mask8()
116 ECLIC_CTRL[irq].INTIE.b.IE = 1; in riscv_clic_irq_enable()
124 ECLIC_CTRL[irq].INTIE.b.IE = 0; in riscv_clic_irq_disable()
132 return ECLIC_CTRL[irq].INTIE.b.IE; in riscv_clic_irq_is_enabled()
149 intattr.b.shv = 0; in riscv_clic_irq_priority_set()
150 intattr.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk); in riscv_clic_irq_priority_set()
162 intattr.b.shv = 1; in riscv_clic_irq_vector_set()
171 ECLIC_CTRL[irq].INTIP.b.IP = 1; in riscv_clic_irq_set_pending()
178 ECLIC_CFG.b.nlbits = 0; in nuclei_eclic_init()
183 nlbits = ECLIC_CFG.b.nlbits; in nuclei_eclic_init()
184 intctlbits = ECLIC_INFO.b.intctlbits; in nuclei_eclic_init()