110 			if (BIT(cb->io_cb.params.wui.bit) & mask) {  in intc_miwu_dispatch_isr()
118 			if (BIT(cb->dev_cb.params.wui.bit) & mask) {  in intc_miwu_dispatch_isr()
122 						   &cb->dev_cb.params.wui);  in intc_miwu_dispatch_isr()
178 void npcx_miwu_irq_enable(const struct npcx_wui *wui)  in npcx_miwu_irq_enable()  argument
180 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_enable()
185 	struct intc_miwu_data *data = miwu_devs[wui->table]->data;  in npcx_miwu_irq_enable()
190 	NPCX_WKEN(base, wui->group) |= BIT(wui->bit);  in npcx_miwu_irq_enable()
193 	if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) {  in npcx_miwu_irq_enable()
194 		npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit);  in npcx_miwu_irq_enable()
200 void npcx_miwu_irq_disable(const struct npcx_wui *wui)  in npcx_miwu_irq_disable()  argument
202 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_disable()
205 	NPCX_WKEN(base, wui->group) &= ~BIT(wui->bit);  in npcx_miwu_irq_disable()
208 void npcx_miwu_io_enable(const struct npcx_wui *wui)  in npcx_miwu_io_enable()  argument
210 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_io_enable()
213 	NPCX_WKINEN(base, wui->group) |= BIT(wui->bit);  in npcx_miwu_io_enable()
216 void npcx_miwu_io_disable(const struct npcx_wui *wui)  in npcx_miwu_io_disable()  argument
218 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_io_disable()
221 	NPCX_WKINEN(base, wui->group) &= ~BIT(wui->bit);  in npcx_miwu_io_disable()
224 bool npcx_miwu_irq_get_state(const struct npcx_wui *wui)  in npcx_miwu_irq_get_state()  argument
226 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_get_state()
229 	return IS_BIT_SET(NPCX_WKEN(base, wui->group), wui->bit);  in npcx_miwu_irq_get_state()
232 bool npcx_miwu_irq_get_and_clear_pending(const struct npcx_wui *wui)  in npcx_miwu_irq_get_and_clear_pending()  argument
234 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_get_and_clear_pending()
238 	struct intc_miwu_data *data = miwu_devs[wui->table]->data;  in npcx_miwu_irq_get_and_clear_pending()
241 	bool pending = IS_BIT_SET(NPCX_WKPND(base, wui->group), wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
247 		NPCX_WKPCL(base, wui->group) = BIT(wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
249 		if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) {  in npcx_miwu_irq_get_and_clear_pending()
250 			npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
254 		NPCX_WKPCL(base, wui->group) = BIT(wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
261 int npcx_miwu_interrupt_configure(const struct npcx_wui *wui,  in npcx_miwu_interrupt_configure()  argument
264 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_interrupt_configure()
266 	uint8_t pmask = BIT(wui->bit);  in npcx_miwu_interrupt_configure()
269 	struct intc_miwu_data *data = miwu_devs[wui->table]->data;  in npcx_miwu_interrupt_configure()
274 	npcx_miwu_irq_disable(wui);  in npcx_miwu_interrupt_configure()
278 	data->both_edge_pins[wui->group] &= ~BIT(wui->bit);  in npcx_miwu_interrupt_configure()
283 		NPCX_WKMOD(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
287 			NPCX_WKEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
291 			NPCX_WKEDG(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
300 		NPCX_WKMOD(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
304 			NPCX_WKAEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
305 			NPCX_WKEDG(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
309 			NPCX_WKAEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
310 			NPCX_WKEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
315 			NPCX_WKAEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
316 			data->both_edge_pins[wui->group] |= BIT(wui->bit);  in npcx_miwu_interrupt_configure()
319 			NPCX_WKAEDG(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
329 	NPCX_WKINEN(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
335 	NPCX_WKPCL(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
338 	if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) {  in npcx_miwu_interrupt_configure()
339 		npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit);  in npcx_miwu_interrupt_configure()
354 	callback->io_cb.params.wui.table = io_wui->table;  in npcx_miwu_init_gpio_callback()
355 	callback->io_cb.params.wui.bit   = io_wui->bit;  in npcx_miwu_init_gpio_callback()
358 	callback->io_cb.params.wui.group = io_wui->group;  in npcx_miwu_init_gpio_callback()
367 	callback->dev_cb.params.wui.table = dev_wui->table;  in npcx_miwu_init_dev_callback()
368 	callback->dev_cb.params.wui.group = dev_wui->group;  in npcx_miwu_init_dev_callback()
369 	callback->dev_cb.params.wui.bit   = dev_wui->bit;  in npcx_miwu_init_dev_callback()
377 	struct npcx_wui *wui;  in npcx_miwu_manage_callback()  local
382 		wui = &cb->io_cb.params.wui;  in npcx_miwu_manage_callback()
384 		wui = &cb->dev_cb.params.wui;  in npcx_miwu_manage_callback()
387 	data = miwu_devs[wui->table]->data;  in npcx_miwu_manage_callback()
388 	cb_list = &data->cb_list_grp[wui->group];  in npcx_miwu_manage_callback()