119 	sys_write32((uint32_t)val, addr);  in arm_gic_write_irouter()
120 	sys_write32((uint32_t)(val >> 32U), addr + 4);  in arm_gic_write_irouter()
143 	sys_write32(mask, ICENABLER(base, idx));  in arm_gic_irq_set_priority()
159 		sys_write32(val, ICFGR(base, idx));  in arm_gic_irq_set_priority()
185 	sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_enable()
199 	sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_disable()
236 	sys_write32(mask, ISPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_set_pending()
244 	sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_clear_pending()
353 	sys_write32(ctlr, rdist + GICR_CTLR);  in gicv3_rdist_setup_lpis()
375 	sys_write32(ctlr, rdist + GICR_CTLR);  in gicv3_rdist_setup_lpis()
392 	sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));  in gicv3_cpuif_init()
397 	sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));  in gicv3_cpuif_init()
403 	sys_write32(IGROUPR_VAL, IGROUPR(base, 0));  in gicv3_cpuif_init()
404 	sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));  in gicv3_cpuif_init()
411 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));  in gicv3_cpuif_init()
415 	sys_write32(0, ICFGR(base, 1));  in gicv3_cpuif_init()
466 	sys_write32(0, GICD_CTLR);  in gicv3_dist_init()
486 		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),  in gicv3_dist_init()
489 		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),  in gicv3_dist_init()
491 		sys_write32(IGROUPR_VAL, IGROUPR(base, idx));  in gicv3_dist_init()
492 		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),  in gicv3_dist_init()
502 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));  in gicv3_dist_init()
509 		sys_write32(0, ICFGR(base, idx));  in gicv3_dist_init()
514 	sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),  in gicv3_dist_init()
527 	sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS),  in gicv3_dist_init()