57 static int gic_wait_rwp(uint32_t intid)  in gic_wait_rwp()  argument
62 	if (intid < GIC_SPI_INT_BASE) {  in gic_wait_rwp()
78 static void arm_gic_lpi_setup(unsigned int intid, bool enable)  in arm_gic_lpi_setup()  argument
80 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_setup()
93 static void arm_gic_lpi_set_priority(unsigned int intid, unsigned int prio)  in arm_gic_lpi_set_priority()  argument
95 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_set_priority()
105 static bool arm_gic_lpi_is_enabled(unsigned int intid)  in arm_gic_lpi_is_enabled()  argument
107 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_is_enabled()
114 static inline void arm_gic_write_irouter(uint64_t val, unsigned int intid)  in arm_gic_write_irouter()  argument
116 	mem_addr_t addr = IROUTER(GET_DIST_BASE(intid), intid);  in arm_gic_write_irouter()
127 void arm_gic_irq_set_priority(unsigned int intid,  in arm_gic_irq_set_priority()  argument
131 	if (intid >= 8192) {  in arm_gic_irq_set_priority()
132 		arm_gic_lpi_set_priority(intid, prio);  in arm_gic_irq_set_priority()
136 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_set_priority()
137 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_set_priority()
140 	mem_addr_t base = GET_DIST_BASE(intid);  in arm_gic_irq_set_priority()
144 	gic_wait_rwp(intid);  in arm_gic_irq_set_priority()
147 	sys_write8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));  in arm_gic_irq_set_priority()
150 	if (!GIC_IS_SGI(intid)) {  in arm_gic_irq_set_priority()
151 		idx = intid / GIC_NUM_CFG_PER_REG;  in arm_gic_irq_set_priority()
152 		shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;  in arm_gic_irq_set_priority()
163 void arm_gic_irq_enable(unsigned int intid)  in arm_gic_irq_enable()  argument
166 	if (intid >= 8192) {  in arm_gic_irq_enable()
167 		arm_gic_lpi_setup(intid, true);  in arm_gic_irq_enable()
171 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_enable()
172 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_enable()
180 	if (GIC_IS_SPI(intid)) {  in arm_gic_irq_enable()
181 		arm_gic_write_irouter(MPIDR_TO_CORE(GET_MPIDR()), intid);  in arm_gic_irq_enable()
185 	sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_enable()
188 void arm_gic_irq_disable(unsigned int intid)  in arm_gic_irq_disable()  argument
191 	if (intid >= 8192) {  in arm_gic_irq_disable()
192 		arm_gic_lpi_setup(intid, false);  in arm_gic_irq_disable()
196 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_disable()
197 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_disable()
199 	sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_disable()
201 	gic_wait_rwp(intid);  in arm_gic_irq_disable()
204 bool arm_gic_irq_is_enabled(unsigned int intid)  in arm_gic_irq_is_enabled()  argument
207 	if (intid >= 8192) {  in arm_gic_irq_is_enabled()
208 		return arm_gic_lpi_is_enabled(intid);  in arm_gic_irq_is_enabled()
211 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_is_enabled()
212 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_is_enabled()
215 	val = sys_read32(ISENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_is_enabled()
220 bool arm_gic_irq_is_pending(unsigned int intid)  in arm_gic_irq_is_pending()  argument
222 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_is_pending()
223 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_is_pending()
226 	val = sys_read32(ISPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_is_pending()
231 void arm_gic_irq_set_pending(unsigned int intid)  in arm_gic_irq_set_pending()  argument
233 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_set_pending()
234 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_set_pending()
236 	sys_write32(mask, ISPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_set_pending()
239 void arm_gic_irq_clear_pending(unsigned int intid)  in arm_gic_irq_clear_pending()  argument
241 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_clear_pending()
242 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_clear_pending()
244 	sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_clear_pending()
249 	int intid;  in arm_gic_get_active()  local
252 	intid = read_sysreg(ICC_IAR1_EL1);  in arm_gic_get_active()
254 	return intid;  in arm_gic_get_active()
257 void arm_gic_eoi(unsigned int intid)  in arm_gic_eoi()  argument
273 	write_sysreg(intid, ICC_EOIR1_EL1);  in arm_gic_eoi()
387 	uint32_t intid;  in gicv3_cpuif_init()  local
409 	for (intid = 0; intid < GIC_SPI_INT_BASE;  in gicv3_cpuif_init()
410 	     intid += GIC_NUM_PRI_PER_REG) {  in gicv3_cpuif_init()
411 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));  in gicv3_cpuif_init()
446 	unsigned int intid;  in gicv3_dist_init()  local
482 	for (intid = GIC_SPI_INT_BASE; intid < num_ints;  in gicv3_dist_init()
483 	     intid += GIC_NUM_INTR_PER_REG) {  in gicv3_dist_init()
484 		idx = intid / GIC_NUM_INTR_PER_REG;  in gicv3_dist_init()
500 	for (intid = GIC_SPI_INT_BASE; intid < num_ints;  in gicv3_dist_init()
501 	     intid += GIC_NUM_PRI_PER_REG) {  in gicv3_dist_init()
502 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));  in gicv3_dist_init()
506 	for (intid = GIC_SPI_INT_BASE; intid < num_ints;  in gicv3_dist_init()
507 	     intid += GIC_NUM_CFG_PER_REG) {  in gicv3_dist_init()
508 		idx = intid / GIC_NUM_CFG_PER_REG;  in gicv3_dist_init()