Lines Matching +full:2 +full:x
41 #define ESP32C3_INTC_SRCS_PER_IRQ 2
49 #define ESP32C6_INTC_SRCS_PER_IRQ 2
55 * - 2, 5, 6, 8 .. 31 are available for Zephyr
61 [2] = {IRQ_FREE, IRQ_FREE},
78 /* in general case, each 2 sources goes routed to in esp_intr_find_irq_for_source()
142 for (int i = 0 ; i < ESP32C3_INTC_AVAILABLE_IRQS + 2; i++) { in esp_intr_initialize()
196 esp_intr_enabled_mask[2] |= (1 << (source - 64)); in esp_intr_alloc()
199 INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", in esp_intr_alloc()
200 esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); in esp_intr_alloc()
237 esp_intr_enabled_mask[2] &= ~(1 << (source - 64)); in esp_intr_disable()
240 INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", in esp_intr_disable()
241 esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); in esp_intr_disable()
271 esp_intr_enabled_mask[2] |= (1 << (source - 64)); in esp_intr_enable()
274 INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", in esp_intr_enable()
275 esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); in esp_intr_enable()
288 INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", in esp_intr_get_enabled_intmask()
289 esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); in esp_intr_get_enabled_intmask()