44 	const TSC_TypeDef *tsc;  member
88 	sys_set_bits((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC | TSC_ICR_MCEIC);  in stm32_tsc_start()
91 	sys_set_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE);  in stm32_tsc_start()
98 	sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_START_Pos);  in stm32_tsc_start()
120 	if (sys_test_bit((mem_addr_t)&config->tsc->ISR, TSC_ISR_MCEF_Pos)) {  in stm32_tsc_handle_incoming_data()
122 		sys_set_bit((mem_addr_t)&config->tsc->ICR, TSC_ICR_MCEIC_Pos);  in stm32_tsc_handle_incoming_data()
124 		LOG_HEXDUMP_DBG(config->tsc, sizeof(TSC_TypeDef), "TSC Registers");  in stm32_tsc_handle_incoming_data()
128 	if (sys_test_bit((mem_addr_t)&config->tsc->ISR, TSC_ISR_EOAF_Pos)) {  in stm32_tsc_handle_incoming_data()
130 		sys_set_bit((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC_Pos);  in stm32_tsc_handle_incoming_data()
137 			if (config->tsc->IOGCSR & group_bit) {  in stm32_tsc_handle_incoming_data()
139 					(mem_addr_t)&config->tsc->IOGXCR[group->group - 1]);  in stm32_tsc_handle_incoming_data()
167 	sys_clear_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE);  in stm32_tsc_isr()
184 	/* reset TSC values to default */  in stm32_tsc_init()
204 	sys_set_bits((mem_addr_t)&config->tsc->CR, (((config->ctph - 1) << 4) | (config->ctpl - 1))  in stm32_tsc_init()
208 	sys_set_bits((mem_addr_t)&config->tsc->CR, config->ssd << TSC_CR_SSD_Pos);  in stm32_tsc_init()
211 	sys_set_bits((mem_addr_t)&config->tsc->CR, config->pgpsc << TSC_CR_PGPSC_Pos);  in stm32_tsc_init()
214 	sys_set_bits((mem_addr_t)&config->tsc->CR, config->max_count << TSC_CR_MCV_Pos);  in stm32_tsc_init()
218 		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSPSC_Pos);  in stm32_tsc_init()
223 		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SYNCPOL_Pos);  in stm32_tsc_init()
228 		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_AM_Pos);  in stm32_tsc_init()
233 		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_IODEF_Pos);  in stm32_tsc_init()
238 		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSE_Pos);  in stm32_tsc_init()
264 			(mem_addr_t)&config->tsc->IOHCR,  in stm32_tsc_init()
268 		sys_set_bits((mem_addr_t)&config->tsc->IOCCR,  in stm32_tsc_init()
272 		sys_set_bits((mem_addr_t)&config->tsc->IOSCR,  in stm32_tsc_init()
277 			sys_set_bit((mem_addr_t)&config->tsc->IOGCSR, group->group - 1);  in stm32_tsc_init()
282 	sys_clear_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE);  in stm32_tsc_init()
285 	sys_set_bits((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC | TSC_ICR_MCEIC);  in stm32_tsc_init()
288 	sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_TSCE_Pos);  in stm32_tsc_init()
322 		.tsc = (TSC_TypeDef *)DT_INST_REG_ADDR(index),                                     \
400 		LOG_ERR("%s: TSC device not ready", config->tsc_dev->name);  in input_tsc_keys_init()