Lines Matching +full:0 +full:x00 +full:- +full:positive
4 * SPDX-License-Identifier: Apache-2.0
27 * Standard registers have 5-bit addresses, BIT[4:0], that range from
28 * 0x00 to 0x1F. For reading, a register address has to be combined with
29 * 0xA0 for reading and 0x80 for writing bits, BIT[7:5].
31 #define PINNACLE_REG_FIRMWARE_ID 0x00 /* R */
32 #define PINNACLE_REG_FIRMWARE_VERSION 0x01 /* R */
33 #define PINNACLE_REG_STATUS1 0x02 /* R/W */
34 #define PINNACLE_REG_SYS_CONFIG1 0x03 /* R/W */
35 #define PINNACLE_REG_FEED_CONFIG1 0x04 /* R/W */
36 #define PINNACLE_REG_FEED_CONFIG2 0x05 /* R/W */
37 #define PINNACLE_REG_FEED_CONFIG3 0x06 /* R/W */
38 #define PINNACLE_REG_CAL_CONFIG1 0x07 /* R/W */
39 #define PINNACLE_REG_PS2_AUX_CONTROL 0x08 /* R/W */
40 #define PINNACLE_REG_SAMPLE_RATE 0x09 /* R/W */
41 #define PINNACLE_REG_Z_IDLE 0x0A /* R/W */
42 #define PINNACLE_REG_Z_SCALER 0x0B /* R/W */
43 #define PINNACLE_REG_SLEEP_INTERVAL 0x0C /* R/W */
44 #define PINNACLE_REG_SLEEP_TIMER 0x0D /* R/W */
45 #define PINNACLE_REG_EMI_THRESHOLD 0x0E /* R/W */
46 #define PINNACLE_REG_PACKET_BYTE0 0x12 /* R */
47 #define PINNACLE_REG_PACKET_BYTE1 0x13 /* R */
48 #define PINNACLE_REG_PACKET_BYTE2 0x14 /* R */
49 #define PINNACLE_REG_PACKET_BYTE3 0x15 /* R */
50 #define PINNACLE_REG_PACKET_BYTE4 0x16 /* R */
51 #define PINNACLE_REG_PACKET_BYTE5 0x17 /* R */
52 #define PINNACLE_REG_GPIO_A_CTRL 0x18 /* R/W */
53 #define PINNACLE_REG_GPIO_A_DATA 0x19 /* R/W */
54 #define PINNACLE_REG_GPIO_B_CTRL_DATA 0x1A /* R/W */
56 #define PINNACLE_REG_ERA_VALUE 0x1B /* R/W */
58 #define PINNACLE_REG_ERA_ADDR_HIGH 0x1C /* R/W */
59 /* Low byte BIT[7:0] of the 16 bit extended register */
60 #define PINNACLE_REG_ERA_ADDR_LOW 0x1D /* R/W */
61 #define PINNACLE_REG_ERA_CTRL 0x1E /* R/W */
62 #define PINNACLE_REG_PRODUCT_ID 0x1F /* R */
65 #define PINNACLE_ERA_REG_CONFIG 0x0187 /* R/W */
68 #define PINNACLE_FIRMWARE_ID 0x07
75 #define PINNACLE_SYS_CONFIG1_RESET BIT(0)
80 #define PINNACLE_FEED_CONFIG1_FEED_ENABLE BIT(0)
87 /* X max to 0 */
89 /* Y max to 0 */
93 #define PINNACLE_FEED_CONFIG2_INTELLIMOUSE_ENABLE BIT(0)
102 #define PINNACLE_PACKET_BYTE0_BTN_PRIMARY BIT(0)
106 #define PINNACLE_ERA_CTRL_READ BIT(0)
110 /* Asserting both BIT(1) and BIT(0) means WRITE/Verify */
111 #define PINNACLE_ERA_CTRL_WRITE_VERIFY (BIT(1) | BIT(0))
112 #define PINNACLE_ERA_CTRL_COMPLETE 0x00
115 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1 0x00
116 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2 0x40
117 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3 0x80
118 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4 0xC0
135 #define PINNACLE_SPI_FB 0xFB /* Filler byte */
136 #define PINNACLE_SPI_FC 0xFC /* Auto-increment byte */
139 #define PINNACLE_READ_MSK 0xA0
140 #define PINNACLE_WRITE_MSK 0x80
217 const struct pinnacle_config *config = dev->config; in pinnacle_bus_is_ready()
219 return config->bus.is_ready(&config->bus); in pinnacle_bus_is_ready()
224 const struct pinnacle_config *config = dev->config; in pinnacle_write()
226 return config->bus.write(&config->bus, address, value); in pinnacle_write()
231 const struct pinnacle_config *config = dev->config; in pinnacle_seq_write()
233 return config->bus.seq_write(&config->bus, address, value, count); in pinnacle_seq_write()
237 const struct pinnacle_config *config = dev->config; in pinnacle_read()
239 return config->bus.read(&config->bus, address, value); in pinnacle_read()
245 const struct pinnacle_config *config = dev->config; in pinnacle_seq_read()
247 return config->bus.seq_read(&config->bus, address, data, count); in pinnacle_seq_read()
252 const struct pinnacle_config *config = dev->config; in pinnacle_clear_cmd_complete()
254 return config->bus.write(&config->bus, PINNACLE_REG_STATUS1, 0x00); in pinnacle_clear_cmd_complete()
262 ret = WAIT_FOR(pinnacle_read(dev, PINNACLE_REG_ERA_CTRL, &value) == 0 && in pinnacle_era_wait_for_completion()
267 return -EIO; in pinnacle_era_wait_for_completion()
270 return 0; in pinnacle_era_wait_for_completion()
284 address & 0xFF, in pinnacle_era_write()
306 address & 0xFF, in pinnacle_era_read()
326 const struct pinnacle_config *config = dev->config; in pinnacle_set_sensitivity()
337 value &= 0x3F; in pinnacle_set_sensitivity()
339 switch (config->sensitivity) { in pinnacle_set_sensitivity()
365 return 0; in pinnacle_set_sensitivity()
371 if (!i2c_is_ready_dt(&bus->i2c)) { in pinnacle_is_ready_i2c()
372 LOG_ERR("I2C bus %s is not ready", bus->i2c.bus->name); in pinnacle_is_ready_i2c()
383 return i2c_write_dt(&bus->i2c, buf, 2); in pinnacle_write_i2c()
391 for (uint8_t i = 0; i < count; ++i) { in pinnacle_seq_write_i2c()
396 return i2c_write_dt(&bus->i2c, buf, count * 2); in pinnacle_seq_write_i2c()
403 return i2c_write_read_dt(&bus->i2c, ®, 1, value, 1); in pinnacle_read_i2c()
411 return i2c_burst_read_dt(&bus->i2c, reg, buf, count); in pinnacle_seq_read_i2c()
418 if (!spi_is_ready_dt(&bus->spi)) { in pinnacle_is_ready_spi()
419 LOG_ERR("SPI bus %s is not ready", bus->spi.bus->name); in pinnacle_is_ready_spi()
441 return spi_write_dt(&bus->spi, &tx_set); in pinnacle_write_spi()
457 for (uint8_t i = 0; i < count; ++i) { in pinnacle_seq_write_spi()
462 return spi_write_dt(&bus->spi, &tx_set); in pinnacle_seq_write_spi()
499 rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set); in pinnacle_read_spi()
501 LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name); in pinnacle_read_spi()
505 return 0; in pinnacle_read_spi()
515 tx_data[0] = PINNACLE_READ_REG(address); in pinnacle_seq_read_spi()
553 rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set); in pinnacle_seq_read_spi()
555 LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name); in pinnacle_seq_read_spi()
559 return 0; in pinnacle_seq_read_spi()
566 const struct pinnacle_config *config = dev->config; in pinnacle_decode_sample()
568 if (config->relative_mode) { in pinnacle_decode_sample()
569 if (config->primary_tap_enabled) { in pinnacle_decode_sample()
570 sample->btn_primary = (rx[0] & BIT(0)) == BIT(0); in pinnacle_decode_sample()
572 sample->rel_x = ((rx[0] & BIT(4)) == BIT(4)) ? -(256 - rx[1]) : rx[1]; in pinnacle_decode_sample()
573 sample->rel_y = ((rx[0] & BIT(5)) == BIT(5)) ? -(256 - rx[2]) : rx[2]; in pinnacle_decode_sample()
575 sample->abs_x = ((rx[2] & 0x0F) << 8) | rx[0]; in pinnacle_decode_sample()
576 sample->abs_y = ((rx[2] & 0xF0) << 4) | rx[1]; in pinnacle_decode_sample()
577 sample->abs_z = rx[3] & 0x3F; in pinnacle_decode_sample()
583 return (sample->abs_x == 0 && sample->abs_y == 0 && sample->abs_z == 0); in pinnacle_is_idle_sample()
588 const struct pinnacle_config *config = dev->config; in pinnacle_clip_sample()
590 if (sample->abs_x < config->active_range_x_min) { in pinnacle_clip_sample()
591 sample->abs_x = config->active_range_x_min; in pinnacle_clip_sample()
593 if (sample->abs_x > config->active_range_x_max) { in pinnacle_clip_sample()
594 sample->abs_x = config->active_range_x_max; in pinnacle_clip_sample()
596 if (sample->abs_y < config->active_range_y_min) { in pinnacle_clip_sample()
597 sample->abs_y = config->active_range_y_min; in pinnacle_clip_sample()
599 if (sample->abs_y > config->active_range_y_max) { in pinnacle_clip_sample()
600 sample->abs_y = config->active_range_y_max; in pinnacle_clip_sample()
606 const struct pinnacle_config *config = dev->config; in pinnacle_scale_sample()
608 uint16_t range_x = config->active_range_x_max - config->active_range_x_min; in pinnacle_scale_sample()
609 uint16_t range_y = config->active_range_y_max - config->active_range_y_min; in pinnacle_scale_sample()
611 sample->abs_x = (uint16_t)((uint32_t)(sample->abs_x - config->active_range_x_min) * in pinnacle_scale_sample()
612 config->resolution_x / range_x); in pinnacle_scale_sample()
613 sample->abs_y = (uint16_t)((uint32_t)(sample->abs_y - config->active_range_y_min) * in pinnacle_scale_sample()
614 config->resolution_y / range_y); in pinnacle_scale_sample()
619 const struct pinnacle_config *config = dev->config; in pinnacle_sample_fetch()
624 if (config->relative_mode) { in pinnacle_sample_fetch()
637 rc = pinnacle_write(dev, PINNACLE_REG_STATUS1, 0x00); in pinnacle_sample_fetch()
643 return 0; in pinnacle_sample_fetch()
648 const struct pinnacle_config *config = dev->config; in pinnacle_handle_interrupt()
649 struct pinnacle_data *drv_data = dev->data; in pinnacle_handle_interrupt()
650 union pinnacle_sample *sample = &drv_data->sample; in pinnacle_handle_interrupt()
660 if (config->relative_mode) { in pinnacle_handle_interrupt()
661 input_report_rel(dev, INPUT_REL_X, sample->rel_x, false, K_FOREVER); in pinnacle_handle_interrupt()
662 input_report_rel(dev, INPUT_REL_Y, sample->rel_y, !config->primary_tap_enabled, in pinnacle_handle_interrupt()
664 if (config->primary_tap_enabled) { in pinnacle_handle_interrupt()
665 input_report_key(dev, INPUT_BTN_TOUCH, sample->btn_primary, true, in pinnacle_handle_interrupt()
669 if (config->clipping_enabled && !pinnacle_is_idle_sample(sample)) { in pinnacle_handle_interrupt()
671 if (config->scaling_enabled) { in pinnacle_handle_interrupt()
676 input_report_abs(dev, INPUT_ABS_X, sample->abs_x, false, K_FOREVER); in pinnacle_handle_interrupt()
677 input_report_abs(dev, INPUT_ABS_Y, sample->abs_y, false, K_FOREVER); in pinnacle_handle_interrupt()
678 input_report_abs(dev, INPUT_ABS_Z, sample->abs_z, true, K_FOREVER); in pinnacle_handle_interrupt()
681 return 0; in pinnacle_handle_interrupt()
689 k_work_submit(&drv_data->work); in pinnacle_data_ready_gpio_callback()
696 pinnacle_handle_interrupt(drv_data->dev); in pinnacle_work_cb()
701 struct pinnacle_data *drv_data = dev->data; in pinnacle_init_interrupt()
702 const struct pinnacle_config *config = dev->config; in pinnacle_init_interrupt()
703 const struct gpio_dt_spec *gpio = &config->dr_gpio; in pinnacle_init_interrupt()
707 drv_data->dev = dev; in pinnacle_init_interrupt()
708 drv_data->work.handler = pinnacle_work_cb; in pinnacle_init_interrupt()
713 LOG_ERR("GPIO device %s/%d is not ready", gpio->port->name, gpio->pin); in pinnacle_init_interrupt()
714 return -ENODEV; in pinnacle_init_interrupt()
719 LOG_ERR("Failed to configure %s/%d as input", gpio->port->name, gpio->pin); in pinnacle_init_interrupt()
725 LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin); in pinnacle_init_interrupt()
729 gpio_init_callback(&drv_data->dr_cb_data, pinnacle_data_ready_gpio_callback, in pinnacle_init_interrupt()
730 BIT(gpio->pin)); in pinnacle_init_interrupt()
732 rc = gpio_add_callback(gpio->port, &drv_data->dr_cb_data); in pinnacle_init_interrupt()
734 LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin); in pinnacle_init_interrupt()
738 return 0; in pinnacle_init_interrupt()
743 const struct pinnacle_config *config = dev->config; in pinnacle_init()
750 return -ENODEV; in pinnacle_init()
761 return -ENODEV; in pinnacle_init()
765 ret = WAIT_FOR(pinnacle_read(dev, PINNACLE_REG_STATUS1, &value) == 0 && in pinnacle_init()
772 return -EIO; in pinnacle_init()
779 return -EIO; in pinnacle_init()
786 return -EIO; in pinnacle_init()
789 rc = pinnacle_write(dev, PINNACLE_REG_SYS_CONFIG1, 0x00); in pinnacle_init()
796 if (config->relative_mode) { in pinnacle_init()
800 if (config->swap_xy) { in pinnacle_init()
803 if (!config->primary_tap_enabled) { in pinnacle_init()
820 if (!config->relative_mode) { in pinnacle_init()
822 if (config->invert_x) { in pinnacle_init()
825 if (config->invert_y) { in pinnacle_init()
835 /* Configure count of Z-Idle packets */ in pinnacle_init()
836 rc = pinnacle_write(dev, PINNACLE_REG_Z_IDLE, config->idle_packets_count); in pinnacle_init()
838 LOG_ERR("Failed to set count of Z-idle packets"); in pinnacle_init()
848 return 0; in pinnacle_init()
864 .spi = SPI_DT_SPEC_INST_GET(inst, PINNACLE_SPI_OP, 0U), \
899 "active-range-x-min must be less than active-range-x-max"); \
902 "active_range-y-min must be less than active_range-y-max"); \
903 BUILD_ASSERT(DT_INST_PROP(inst, scaling_x_resolution) > 0, \
904 "scaling-x-resolution must be positive"); \
905 BUILD_ASSERT(DT_INST_PROP(inst, scaling_y_resolution) > 0, \
906 "scaling-y-resolution must be positive"); \
907 BUILD_ASSERT(IN_RANGE(DT_INST_PROP(inst, idle_packets_count), 0, UINT8_MAX), \
908 "idle-packets-count must be in range [0:255]");