Lines Matching refs:BIT
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
119 #define MCR20A_IRQSTS1_RX_FRM_PEND BIT(7)
120 #define MCR20A_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
121 #define MCR20A_IRQSTS1_FILTERFAIL_IRQ BIT(5)
122 #define MCR20A_IRQSTS1_RXWTRMRKIRQ BIT(4)
123 #define MCR20A_IRQSTS1_CCAIRQ BIT(3)
124 #define MCR20A_IRQSTS1_RXIRQ BIT(2)
125 #define MCR20A_IRQSTS1_TXIRQ BIT(1)
126 #define MCR20A_IRQSTS1_SEQIRQ BIT(0)
129 #define MCR20A_IRQSTS2_CRCVALID BIT(7)
130 #define MCR20A_IRQSTS2_CCA BIT(6)
131 #define MCR20A_IRQSTS2_SRCADDR BIT(5)
132 #define MCR20A_IRQSTS2_PI BIT(4)
133 #define MCR20A_IRQSTS2_TMRSTATUS BIT(3)
134 #define MCR20A_IRQSTS2_ASM_IRQ BIT(2)
135 #define MCR20A_IRQSTS2_PB_ERR_IRQ BIT(1)
136 #define MCR20A_IRQSTS2_WAKE_IRQ BIT(0)
139 #define MCR20A_IRQSTS3_TMR4MSK BIT(7)
140 #define MCR20A_IRQSTS3_TMR3MSK BIT(6)
141 #define MCR20A_IRQSTS3_TMR2MSK BIT(5)
142 #define MCR20A_IRQSTS3_TMR1MSK BIT(4)
144 #define MCR20A_IRQSTS3_TMR4IRQ BIT(3)
145 #define MCR20A_IRQSTS3_TMR3IRQ BIT(2)
146 #define MCR20A_IRQSTS3_TMR2IRQ BIT(1)
147 #define MCR20A_IRQSTS3_TMR1IRQ BIT(0)
151 #define MCR20A_PHY_CTRL1_TMRTRIGEN BIT(7)
152 #define MCR20A_PHY_CTRL1_SLOTTED BIT(6)
153 #define MCR20A_PHY_CTRL1_CCABFRTX BIT(5)
154 #define MCR20A_PHY_CTRL1_RXACKRQD BIT(4)
155 #define MCR20A_PHY_CTRL1_AUTOACK BIT(3)
166 #define MCR20A_PHY_CTRL2_CRC_MSK BIT(7)
167 #define MCR20A_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6)
168 #define MCR20A_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
169 #define MCR20A_PHY_CTRL2_RX_WMRK_MSK BIT(4)
170 #define MCR20A_PHY_CTRL2_CCAMSK BIT(3)
171 #define MCR20A_PHY_CTRL2_RXMSK BIT(2)
172 #define MCR20A_PHY_CTRL2_TXMSK BIT(1)
173 #define MCR20A_PHY_CTRL2_SEQMSK BIT(0)
175 #define MCR20A_PHY_CTRL3_TMR4CMP_EN BIT(7)
176 #define MCR20A_PHY_CTRL3_TMR3CMP_EN BIT(6)
177 #define MCR20A_PHY_CTRL3_TMR2CMP_EN BIT(5)
178 #define MCR20A_PHY_CTRL3_TMR1CMP_EN BIT(4)
179 #define MCR20A_PHY_CTRL3_ASM_MSK BIT(2)
180 #define MCR20A_PHY_CTRL3_PB_ERR_MSK BIT(1)
181 #define MCR20A_PHY_CTRL3_WAKE_MSK BIT(0)
185 #define MCR20A_PHY_CTRL4_TRCV_MSK BIT(7)
186 #define MCR20A_PHY_CTRL4_TC3TMOUT BIT(6)
187 #define MCR20A_PHY_CTRL4_PANCORDNTR0 BIT(5)
190 #define MCR20A_PHY_CTRL4_TMRLOAD BIT(2)
191 #define MCR20A_PHY_CTRL4_PROMISCUOUS BIT(1)
192 #define MCR20A_PHY_CTRL4_TC2PRIME_EN BIT(0)
196 #define MCR20A_SRC_CTRL_ACK_FRM_PND BIT(3)
197 #define MCR20A_SRC_CTRL_SRCADDR_EN BIT(2)
198 #define MCR20A_SRC_CTRL_INDEX_EN BIT(1)
199 #define MCR20A_SRC_CTRL_INDEX_DISABLE BIT(0)
209 #define MCR20A_ASM_CTRL1_CLEAR BIT(7)
210 #define MCR20A_ASM_CTRL1_START BIT(6)
211 #define MCR20A_ASM_CTRL1_SELFTST BIT(5)
212 #define MCR20A_ASM_CTRL1_CTR BIT(4)
213 #define MCR20A_ASM_CTRL1_CBC BIT(3)
214 #define MCR20A_ASM_CTRL1_AES BIT(2)
215 #define MCR20A_ASM_CTRL1_LOAD_MAC BIT(1)
219 #define MCR20A_ASM_CTRL2_TSTPAS BIT(1)
221 #define MCR20A_CLK_OUT_EXTEND BIT(7)
222 #define MCR20A_CLK_OUT_HIZ BIT(6)
223 #define MCR20A_CLK_OUT_SR BIT(5)
224 #define MCR20A_CLK_OUT_DS BIT(4)
225 #define MCR20A_CLK_OUT_EN BIT(3)
229 #define MCR20A_PWR_MODES_XTAL_READY BIT(5)
230 #define MCR20A_PWR_MODES_XTALEN BIT(4)
231 #define MCR20A_PWR_MODES_ASM_CLK_EN BIT(3)
232 #define MCR20A_PWR_MODES_AUTODOZE BIT(1)
233 #define MCR20A_PWR_MODES_PMC_MODE BIT(0)
417 #define MCR20A_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS BIT(5)
418 #define MCR20A_RX_FRAME_FILTER_NS_FT BIT(4)
419 #define MCR20A_RX_FRAME_FILTER_CMD_FT BIT(3)
420 #define MCR20A_RX_FRAME_FILTER_ACK_FT BIT(2)
421 #define MCR20A_RX_FRAME_FILTER_DATA_FT BIT(1)
422 #define MCR20A_RX_FRAME_FILTER_BEACON_FT BIT(0)
428 #define MCR20A_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3)
429 #define MCR20A_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2)
430 #define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1)
431 #define MCR20A_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0)
433 #define MCR20A_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7)
434 #define MCR20A_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6)
437 #define MCR20A_CCA_CTRL_AGC_FRZ_EN BIT(6)
438 #define MCR20A_CCA_CTRL_CONT_RSSI_EN BIT(5)
439 #define MCR20A_CCA_CTRL_QI_RSSI_NOT_CORR BIT(4)
440 #define MCR20A_CCA_CTRL_CCA3_AND_NOT_OR BIT(3)
441 #define MCR20A_CCA_CTRL_OWER_COMP_EN_LQI BIT(2)
442 #define MCR20A_CCA_CTRL_OWER_COMP_EN_ED BIT(1)
443 #define MCR20A_CCA_CTRL_OWER_COMP_EN_CCA1 BIT(0)
459 #define MCR20A_GPIO_DATA8 BIT(7)
460 #define MCR20A_GPIO_DATA7 BIT(6)
461 #define MCR20A_GPIO_DATA6 BIT(5)
462 #define MCR20A_GPIO_DATA5 BIT(4)
463 #define MCR20A_GPIO_DATA4 BIT(3)
464 #define MCR20A_GPIO_DATA3 BIT(2)
465 #define MCR20A_GPIO_DATA2 BIT(1)
466 #define MCR20A_GPIO_DATA1 BIT(0)
468 #define MCR20A_GPIO_DIR8 BIT(7)
469 #define MCR20A_GPIO_DIR7 BIT(6)
470 #define MCR20A_GPIO_DIR6 BIT(5)
471 #define MCR20A_GPIO_DIR5 BIT(4)
472 #define MCR20A_GPIO_DIR4 BIT(3)
473 #define MCR20A_GPIO_DIR3 BIT(2)
474 #define MCR20A_GPIO_DIR2 BIT(1)
475 #define MCR20A_GPIO_DIR1 BIT(0)
477 #define MCR20A_GPIO_PUL_EN8 BIT(7)
478 #define MCR20A_GPIO_PUL_EN7 BIT(6)
479 #define MCR20A_GPIO_PUL_EN6 BIT(5)
480 #define MCR20A_GPIO_PUL_EN5 BIT(4)
481 #define MCR20A_GPIO_PUL_EN4 BIT(3)
482 #define MCR20A_GPIO_PUL_EN3 BIT(2)
483 #define MCR20A_GPIO_PUL_EN2 BIT(1)
484 #define MCR20A_GPIO_PUL_EN1 BIT(0)
486 #define MCR20A_GPIO_PUL_SEL8 BIT(7)
487 #define MCR20A_GPIO_PUL_SEL7 BIT(6)
488 #define MCR20A_GPIO_PUL_SEL6 BIT(5)
489 #define MCR20A_GPIO_PUL_SEL5 BIT(4)
490 #define MCR20A_GPIO_PUL_SEL4 BIT(3)
491 #define MCR20A_GPIO_PUL_SEL3 BIT(2)
492 #define MCR20A_GPIO_PUL_SEL2 BIT(1)
493 #define MCR20A_GPIO_PUL_SEL1 BIT(0)
495 #define MCR20A_GPIO_DS8 BIT(7)
496 #define MCR20A_GPIO_DS7 BIT(6)
497 #define MCR20A_GPIO_DS6 BIT(5)
498 #define MCR20A_GPIO_DS5 BIT(4)
499 #define MCR20A_GPIO_DS4 BIT(3)
500 #define MCR20A_GPIO_DS3 BIT(2)
501 #define MCR20A_GPIO_DS2 BIT(1)
502 #define MCR20A_GPIO_DS1 BIT(0)
504 #define MCR20A_ANT_PAD_CTRL_ANTX_POL3 BIT(7)
505 #define MCR20A_ANT_PAD_CTRL_ANTX_POL2 BIT(6)
506 #define MCR20A_ANT_PAD_CTRL_ANTX_POL1 BIT(5)
507 #define MCR20A_ANT_PAD_CTRL_ANTX_POL0 BIT(4)
508 #define MCR20A_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3)
509 #define MCR20A_ANT_PAD_CTRL_ANTX_HZ BIT(2)
513 #define MCR20A_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3)
514 #define MCR20A_MISC_PAD_CTRL_IRQ_B_OD BIT(2)
515 #define MCR20A_MISC_PAD_CTRL_NON_GPIO_DS BIT(1)
516 #define MCR20A_MISC_PAD_CTRL_ANTX_CURR BIT(0)
518 #define MCR20A_ANT_AGC_CTRL_SNF_EN BIT(7)
519 #define MCR20A_ANT_AGC_CTRL_AGC_EN BIT(6)
522 #define MCR20A_ANT_AGC_CTRL_ANTX BIT(1)
523 #define MCR20A_ANT_AGC_CTRL_AD_EN BIT(0)
525 #define MCR20A_LPPS_BUFMIX_EN BIT(4)
526 #define MCR20A_LPPS_LIM_EN BIT(3)
527 #define MCR20A_LPPS_RSSI_EN BIT(2)
528 #define MCR20A_LPPS_LNA_EN BIT(1)
529 #define MCR20A_LPPS_CTRL_LPPS_EN BIT(0)
532 #define MCR20A_SOFT_RESET_SOG_RST BIT(7)
533 #define MCR20A_SOFT_RESET_REGS_RST BIT(4)
534 #define MCR20A_SOFT_RESET_PLL_RST BIT(3)
535 #define MCR20A_SOFT_RESET_TX_RST BIT(2)
536 #define MCR20A_SOFT_RESET_RX_RST BIT(1)
537 #define MCR20A_SOFT_RESET_SEQ_MGR_RST BIT(0)
541 #define MCR20A_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
542 #define MCR20A_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
543 #define MCR20A_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3)
544 #define MCR20A_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2)
545 #define MCR20A_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1)
546 #define MCR20A_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0)
548 #define MCR20A_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7)
549 #define MCR20A_SEQ_MGR_STS_RX_MODE BIT(6)
550 #define MCR20A_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
551 #define MCR20A_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
552 #define MCR20A_SEQ_MGR_STS_SEQ_IDLE BIT(3)
556 #define MCR20A_ABORT_STS_PLL_ABORTED BIT(2)
557 #define MCR20A_ABORT_STS_TC3_ABORTED BIT(1)
558 #define MCR20A_ABORT_STS_SW_ABORTED BIT(0)
560 #define MCR20A_PHY_STS_PLL_UNLOCK BIT(7)
561 #define MCR20A_PHY_STS_PLL_LOCK_ERR BIT(6)
562 #define MCR20A_PHY_STS_PLL_LOCK BIT(5)
563 #define MCR20A_PHY_STS_CRCVALID BIT(3)
564 #define MCR20A_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2)
565 #define MCR20A_PHY_STS_SFD_DET BIT(1)
566 #define MCR20A_PHY_STS_PREAMBLE_DET BIT(0)
568 #define MCR20A_TESTMODE_CTRL_HOT_ANT BIT(4)
569 #define MCR20A_TESTMODE_CTRL_IDEAL_RSSI_EN BIT(3)
570 #define MCR20A_TESTMODE_CTRL_IDEAL_PFC_EN BIT(2)
571 #define MCR20A_TESTMODE_CTRL_CONTINUOUS_EN BIT(1)
572 #define MCR20A_TESTMODE_CTRL_FPGA_EN BIT(0)
574 #define MCR20A_DTM_CTRL1_ATM_LOCKED BIT(7)
575 #define MCR20A_DTM_CTRL1_DTM_EN BIT(6)
576 #define MCR20A_DTM_CTRL1_PAGE5 BIT(5)
577 #define MCR20A_DTM_CTRL1_PAGE4 BIT(4)
578 #define MCR20A_DTM_CTRL1_PAGE3 BIT(3)
579 #define MCR20A_DTM_CTRL1_PAGE2 BIT(2)
580 #define MCR20A_DTM_CTRL1_PAGE1 BIT(1)
581 #define MCR20A_DTM_CTRL1_PAGE0 BIT(0)
583 #define MCR20A_TX_MODE_CTRL_TX_INV BIT(4)
584 #define MCR20A_TX_MODE_CTRL_BT_EN BIT(3)
585 #define MCR20A_TX_MODE_CTRL_DTS2 BIT(2)
586 #define MCR20A_TX_MODE_CTRL_DTS1 BIT(1)
587 #define MCR20A_TX_MODE_CTRL_DTS0 BIT(0)