615 				  uint8_t *dregs)  in irqsts1_event()  argument
618 	uint8_t seq = dregs[MCR20A_PHY_CTRL1] & MCR20A_PHY_CTRL1_XCVSEQ_MASK;  in irqsts1_event()
624 		if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_RXIRQ)) {  in irqsts1_event()
625 			if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_TXIRQ)) {  in irqsts1_event()
631 			mcr20a_rx(dev, dregs[MCR20A_RX_FRM_LEN]);  in irqsts1_event()
637 		if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_CCAIRQ) {  in irqsts1_event()
638 			if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_CCA) {  in irqsts1_event()
646 		if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_TXIRQ) {  in irqsts1_event()
649 			if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_RXIRQ)) {  in irqsts1_event()
662 		if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_CCAIRQ)) {  in irqsts1_event()
667 			if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_CCA) {  in irqsts1_event()
687 		LOG_ERR("IRQSTS: 0x%02x", dregs[MCR20A_IRQSTS1]);  in irqsts1_event()
691 	dregs[MCR20A_PHY_CTRL1] &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;  in irqsts1_event()
692 	dregs[MCR20A_PHY_CTRL1] |= new_seq;  in irqsts1_event()
703 				 uint8_t *dregs)  in irqsts3_event()  argument
708 	if (dregs[MCR20A_IRQSTS3] & MCR20A_IRQSTS3_TMR4IRQ) {  in irqsts3_event()
710 			    dregs[MCR20A_IRQSTS1],  in irqsts3_event()
711 			    dregs[MCR20A_IRQSTS2],  in irqsts3_event()
712 			    dregs[MCR20A_IRQSTS3]);  in irqsts3_event()
716 		dregs[MCR20A_PHY_CTRL1] &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;  in irqsts3_event()
717 		dregs[MCR20A_PHY_CTRL1] |= MCR20A_XCVSEQ_RECEIVE;  in irqsts3_event()
720 		dregs[MCR20A_IRQSTS1] = MCR20A_IRQSTS1_IRQ_MASK;  in irqsts3_event()
724 			    dregs[MCR20A_IRQSTS3]);  in irqsts3_event()
737 	uint8_t dregs[MCR20A_PHY_CTRL4 + 1];  in mcr20a_thread_main()  local
753 		if (!read_burst_irqsts1_ctrl4(dev, dregs)) {  in mcr20a_thread_main()
758 		ctrl1 = dregs[MCR20A_PHY_CTRL1];  in mcr20a_thread_main()
760 		if (dregs[MCR20A_IRQSTS3] & MCR20A_IRQSTS3_IRQ_MASK) {  in mcr20a_thread_main()
761 			set_new_seq = irqsts3_event(dev, dregs);  in mcr20a_thread_main()
762 		} else if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_SEQIRQ) {  in mcr20a_thread_main()
763 			set_new_seq = irqsts1_event(dev, dregs);  in mcr20a_thread_main()
766 		if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_IRQ_MASK) {  in mcr20a_thread_main()
768 				    dregs[MCR20A_IRQSTS2]);  in mcr20a_thread_main()
772 			     dregs[MCR20A_IRQSTS1],  in mcr20a_thread_main()
773 			     dregs[MCR20A_IRQSTS2],  in mcr20a_thread_main()
774 			     dregs[MCR20A_IRQSTS3]);  in mcr20a_thread_main()
786 			if (!write_burst_irqsts1_ctrl1(dev, dregs)) {  in mcr20a_thread_main()
790 			if (!write_burst_irqsts1_irqsts3(dev, dregs)) {  in mcr20a_thread_main()