273 	uint8_t ctrl4 = read_reg_phy_ctrl4(dev);  in mcr20a_mask_irqb()  local
276 		ctrl4 |= MCR20A_PHY_CTRL4_TRCV_MSK;  in mcr20a_mask_irqb()
278 		ctrl4 &= ~MCR20A_PHY_CTRL4_TRCV_MSK;  in mcr20a_mask_irqb()
281 	return write_reg_phy_ctrl4(dev, ctrl4);  in mcr20a_mask_irqb()
333 	uint8_t ctrl4;  in mcr20a_timer_init()  local
344 	ctrl4 = read_reg_phy_ctrl4(dev);  in mcr20a_timer_init()
345 	ctrl4 |= MCR20A_PHY_CTRL4_TMRLOAD;  in mcr20a_timer_init()
346 	if (!write_reg_phy_ctrl4(dev, ctrl4)) {  in mcr20a_timer_init()
841 	uint8_t ctrl4;  in mcr20a_set_cca_mode()  local
843 	ctrl4 = read_reg_phy_ctrl4(dev);  in mcr20a_set_cca_mode()
844 	ctrl4 &= ~MCR20A_PHY_CTRL4_CCATYPE_MASK;  in mcr20a_set_cca_mode()
845 	ctrl4 |= set_bits_phy_ctrl4_ccatype(mode);  in mcr20a_set_cca_mode()
847 	if (!write_reg_phy_ctrl4(dev, ctrl4)) {  in mcr20a_set_cca_mode()